SRAM Power Switch Voltage Reduction Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor device technologies face challenges in enhancing the write margin without degrading the static noise margin, and they often result in increased physical circuit size due to the need for additional components like coupling capacitance elements and logic gates.
Innovation Solution
The implementation of a power switch for each power supply line with a short-circuit switch to provide voltage reduction during write operations, eliminating the need for logic gates and minimizing circuit size by using complementary bit line select signals for control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If coupling capacitance elements are used to reduce power supply voltage in write operations, then write margin is enhanced, but chip occupancy area increases
Solution Approach 1:
The patent extracts the voltage reduction function from dedicated coupling capacitance elements and implements it through the interaction of existing power switches and bit line capacitances. By removing the need for separate coupling capacitance elements, the invention reduces chip area while maintaining write margin enhancement capability
Solution Approach 2:
The patent makes the power switches serve multiple functions: they control power supply voltage during both read and write operations, and their interaction with bit line capacitances provides the voltage reduction effect previously requiring separate coupling capacitance elements. This multi-functionality eliminates additional area requirements
2Reliability
If logical AND gates are provided for each power supply line to control power switches, then write margin is enhanced, but area overhead increases
Solution Approach 1:
The patent merges the logical AND function into the power switch control circuitry itself. The power switches are controlled by signals that inherently combine the select signal and write operation indication, eliminating the need for separate logical AND gates for each power supply line
Solution Approach 2:
The power switches automatically respond to write operations by detecting the appropriate signal conditions and reducing power supply voltage without requiring external logical AND gates. The control system self-manages the voltage reduction function through the inherent behavior of the power switches
Data Source
AI summary
Disclosed is a semiconductor device in which substantial enhancement of a write margin without degradation of a static noise can be achieved while obviating an increase in physical circuit size. There are disposed a plurality of power supply lines for feeding a power supply voltage to each column of static memory cells that use complementary bit lines in common; a plurality of power switches, each being disposed for each of the power supply lines; and a plurality of short-circuit switches, each being so arranged as to provide short-circuiting between output nodes of different power switches. When a complementary bit line select signal indicates an unselected level, the power switch corresponding thereto is put in an ON state so that, in a read operation, a power supply voltage is fed via the short-circuit switch concerned to a selected memory cell column from the power supply line corresponding to a memory cell being unselected, or in a write operation, a power supply voltage fed via the short-circuit switch concerned to a selected memory cell column is stopped.