SRAM PUF Bit Screening Using Trip-Point Tilting
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Solution Overview
Problem
Existing SRAM PUFs in transistor circuitry are vulnerable to noise and environmental effects, leading to unreliable bits, which compromise security and require error correction codes that expose secure information, resulting in limited reliability and security concerns.
Innovation Solution
A tilting method is employed to expose unstable bits by applying a biasing technique to the PUF trip point, using differential supply voltages to distinguish between stable and unstable cells, and optionally incorporating a Miller capacitor to neutralize parasitic effects, allowing for the identification and elimination of unstable bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If SRAM PUF is used to generate digital identifiers, then uniqueness is improved, but reliability deteriorates due to noise and environmental effects
Solution Approach 1:
The patent applies preliminary action by performing burn-in processing before the PUF operates in normal mode. This burn-in phase stabilizes the intrinsic variations in the semiconductor devices, ensuring that the PUF output becomes reliable and repeatable under subsequent environmental conditions while maintaining uniqueness.
Solution Approach 2:
The patent employs parameter changes by utilizing different operating conditions (temperature, voltage) to characterize the PUF behavior. By measuring the PUF output across multiple PVT corners and analyzing the stability of the output, the system can distinguish between unique but unstable bits and truly reliable bits, thereby improving reliability while preserving uniqueness.
2Reliability
If error correction codes are used to compensate for unstable bits, then reliability is improved, but security deteriorates by exposing secure information
Solution Approach 1:
The patent extracts and eliminates unstable bits from the PUF array through a screening process. By identifying bits that produce inconsistent outputs across different PVT conditions and removing them from the secure key generation process, the system achieves reliability improvement without needing to expose secure information through error correction codes.
3Reliability
If temporal majority voting is used to identify stable bits, then reliability is improved, but complexity increases
Solution Approach 1:
The patent performs preliminary characterization of the PUF array under multiple PVT conditions to identify stable and unstable bits before normal operation. This upfront screening process, which involves measuring the PUF output at different temperature and voltage corners, reduces the complexity during normal operation by pre-determining which bits can be trusted, avoiding the need for continuous majority voting mechanisms.
Data Source
AI summary
A method for detecting unreliable bits in transistor circuitry includes applying a controllable physical parameter to a transistor circuitry, thereby causing a variation in a digital code of a cryptologic element in the transistor circuitry, the variation being a tilt or bias in a positive or negative direction. An amount of variation in the digital code of the cryptologic element is determined. Unreliable bits in the transistor circuitry are defined as those bits for which the variation is in a range defined as unreliable.