SRAM Read-Port Voltage Separation for Faster Stable Reads
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Solution Overview
Problem
Conventional SRAM designs face a trade-off between reading speed and stability due to the shared voltage source connection affecting latch circuit stability during reading operations, leading to potential data loss and increased leakage current.
Innovation Solution
The SRAM design separates the voltage sources for the pull-down transistors and the read port transistor, allowing independent control of voltage potentials to enhance reading speed without compromising stability by maintaining separate voltage sources Vss1 and Vss2, with Vss2 being set to a negative potential during reading and a positive potential during standby.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the voltage source Vss is shared among pull-down transistors and read port transistor, then the circuit structure is simple, but the reading speed is reduced and latch circuit stability deteriorates
Solution Approach 1:
The patent divides the originally shared voltage source Vss into two separate voltage sources: Vss1 connected to the pull-down transistors and Vss2 connected to the read port transistor. This segmentation allows independent voltage control for each transistor group, enabling faster reading by adjusting Vss2 without affecting the stability of the latch circuit connected to Vss1.
Solution Approach 2:
The patent implements dynamic voltage control where Vss2 can be independently adjusted during read operations to optimize reading speed, while Vss1 maintains stable operation of the latch circuit. This dynamic separation allows the system to adapt voltage levels based on operational requirements.
2Speed
If the voltage potential of Vss is lowered to enhance reading speed, then the reading speed improves, but the latch circuit stability deteriorates due to potential fluctuations
Solution Approach 1:
By separating the voltage sources, the patent isolates the latch circuit (connected to Vss1) from the read port transistor (connected to Vss2). This allows Vss2 to be lowered to enhance reading speed while Vss1 remains stable, preventing potential fluctuations from affecting latch circuit stability.
Solution Approach 2:
The separate voltage source Vss1 acts as an intermediary that stabilizes the latch circuit while Vss2 handles the read operation voltage adjustments. This intermediary voltage source prevents direct coupling between read operations and latch circuit potential.
3Speed
If the voltage source connection is separated to enhance reading speed, then the reading speed improves, but the leakage current increases during standby state
Solution Approach 1:
The patent implements dynamic voltage control where Vss2 can be adjusted based on operational state: lowered during read operations to enhance speed, and raised during standby state to reduce leakage current. This dynamic adjustment optimizes both performance and power consumption.
Solution Approach 2:
The patent changes the voltage parameter of Vss2 dynamically - lowering it during read operations to improve speed and raising it during standby operations to minimize leakage current. This parameter adjustment resolves the contradiction between speed enhancement and leakage reduction.
Data Source
AI summary
The invention provides a layout pattern of static random access memory, which comprises a plurality of fin structures on a substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate. The transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2), a first access transistor (PG1), a second access transistor (PG2), a first read port transistor (RPD) and a second read port transistor (RPG). The gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1), wherein a drain of the first pull-down transistor (PD1) is connected to a first voltage source Vss1, and a drain of the first read port transistor (RPD) is connected to a second voltage source Vss2.