SRAM-ROM Cell Layout for Reduced Memory Area

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Solution Overview

Problem

Existing combination memory devices do not effectively reduce the area of the memory cell region, which is a significant factor in determining the size of semiconductor chips, as they lack an optimized layout for integrating SRAM and ROM cells.

Innovation Solution

The proposed solution involves arranging SRAM and ROM cells in a zigzag pattern, where each SRAM cell includes a ROM cell on its boundary, sharing a common word line, and using separate bit lines for SRAM and ROM operations to minimize area and reduce peripheral circuitry, allowing the ROM cell to be placed in the free space of the SRAM cell.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If SRAM and ROM cells are arranged in a conventional layout, then manufacturing is simplified, but the memory cell region area cannot be reduced

Engineering Contradiction:
Improvelayout simplicityVSAvoidmemory cell region area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

Different memory cells are given different local qualities: first memory cells contain both SRAM and ROM cells with shared boundary regions, while second memory cells contain only SRAM cells. This local differentiation allows optimized space utilization in the boundary regions of first memory cells, reducing the overall memory cell region area while maintaining manufacturing feasibility through standardized cell structures.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8081525B2Memory device including combination SRAM-ROM cells and SRAM cells alternately arranged and semiconductor device including the memory device
Publication Date: 2011.12.20 PANASONIC SEMICON SOLUTIONS CO LTD
  • US8081525B2 patent drawing
  • US8081525B2 patent drawing
  • US8081525B2 patent drawing

AI summary

A combination memory device including a static random access memory (SRAM) and a read only memory (ROM) comprises first memory cells and second memory cells arranged in rows and columns, in which each of the first memory cells includes an SRAM cell and a ROM cell and is arranged adjacent to at least one of the second memory cells, and each of the second memory cells includes an SRAM cell and does not include a ROM cell.