SRAM ROM Memory Reconfigurable by Substrate Polarisation

The patent extracts the mode selection functionality from the control circuitry and embeds it within the memory cell structure itself. By incorporating selection transistors directly in the memory cell that respond to bias line potentials, the mode switching capability is moved from external control circuits into the cell architecture, thereby reducing the need for substantial modifications to word line drivers and control logic.

The patent introduces bias lines as intermediary elements that mediate between the control logic and the memory cell transistors. These bias lines carry potentials that selectively activate or deactivate specific transistors within the memory cell, enabling mode switching without requiring direct modification of the existing word line control circuitry. The bias lines act as a buffer layer that simplifies the interface between control logic and cell operation.

The patent merges ROM and SRAM functionalities into a unified memory cell structure. The same physical memory cell can operate in either SRAM mode (with all transistors active) or ROM mode (with selection transistors activating specific paths), eliminating the need for separate ROM and SRAM cell structures. This consolidation maintains high integration density while providing dual functionality.

The memory cell is designed with universal transistors that can serve multiple functions depending on bias conditions. The selection transistors, when activated by specific bias line potentials, enable the cell to function as a ROM cell with predetermined data, while in other bias states the same cell operates as a fully writable SRAM cell. This multi-functionality approach maximizes memory versatility without sacrificing integration density.