SRAM Error Detection via Segmented Scrubbing
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Solution Overview
Problem
Processing systems, such as those in automobiles, face data corruption issues due to external conditions like cosmic rays, leading to errors in critical operations and reduced reliability.
Innovation Solution
The implementation of a processing system with a static random-access memory (SRAM) partitioned into critical and non-critical domains, where a memory scrubbing circuitry uses finite state machines and error correction codes to detect and correct single-bit and multi-bit memory errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read-only memory is used to store critical operation data, then data integrity is improved, but vulnerability to cosmic ray corruption remains
Solution Approach 1:
The memory system is segmented into critical domain memory banks and non-critical domain memory banks, with separate access control and error detection mechanisms. Each memory bank is independently managed with dedicated scrubbing circuits that operate separately, allowing error detection in critical memory without affecting non-critical operations.
Solution Approach 2:
Error detection and correction codes serve as an intermediary layer between the physical memory storage and the critical operations. The scrubbing circuitry acts as a mediator that continuously monitors and corrects errors in the memory data before it can affect critical operations, thereby protecting against cosmic ray corruption.
2Productivity
If SRAM is shared between critical and non-critical domains, then memory efficiency is improved, but error propagation risk increases
Solution Approach 1:
The shared SRAM is divided into separately accessible critical and non-critical domains with distinct access control logic. The memory arbiter segments memory access paths, allowing simultaneous or sequential access by different domains while preventing unauthorized writes to critical memory banks from the non-critical domain.
Solution Approach 2:
Different quality levels of protection are applied to different memory regions. Critical memory banks have enhanced error detection and correction capabilities with dedicated scrubbing circuits, while non-critical memory banks use standard protection. This local differentiation allows efficient error prevention in critical areas without sacrificing overall memory efficiency.
3Measurement precision
If memory scrubbing circuitry is implemented, then error detection capability is improved, but system complexity increases
Solution Approach 1:
The scrubbing circuitry is segmented into multiple independent finite state machines, each responsible for scrubbing specific memory banks. This segmentation allows parallel error detection operations and simplifies the design of individual scrubbing units compared to a monolithic scrubbing system.
Solution Approach 2:
The memory scrubbing system operates autonomously using dedicated finite state machines that automatically detect and correct errors without requiring intervention from the main processing logic. The scrubbing circuits self-manage the error detection and correction process, reducing the complexity burden on the main system controller.
4Extent of automation
If finite state machines are used for memory scrubbing, then automation level is improved, but resource consumption increases
Solution Approach 1:
The finite state machines perform memory scrubbing operations periodically rather than continuously, scrubbing memory banks at scheduled intervals. This periodic operation reduces resource consumption compared to continuous monitoring while maintaining effective error detection capability. The scrubbing operation is triggered by scrubbing requests and completes within defined state transitions.
Data Source
AI summary
A system on a chip (SOC) includes a critical domain including components configured to perform critical operations and a non-critical domain including components configured to perform non-critical operations. To help perform such operations, the critical domain and non-critical domain share a static random-access memory (SRAM) that includes a first subset of memory banks assigned to the critical domain and a second subset of memory banks assigned to the non-critical domain. The SOC further includes a memory scrubbing circuitry configured to sequentially check each memory bank of the SRAM for errors. To this end, the memory scrubbing circuitry is configured to check a respective memory bank for errors each time an event trigger occurs by implementing one or more error correction codes.