Triggered SRAM Sense Amplifier Timing for Accurate Low-Power Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional sense amplifiers in SRAM implementations are prone to errors due to incorrect detection of differential signals and wasteful power consumption, as they operate in a constant state of detection with continuous current sourcing.
Innovation Solution
A programmable logic device (PLD) with SRAM cells connected to bitlines, where a sense amplifier detects data values only after a trigger signal is delayed relative to the wordline signal, allowing data signals to settle, thereby improving accuracy and reducing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional sense amplifiers operate in a constant state of detection with continuous current sourcing, then they can continuously detect data values, but power consumption increases and detection accuracy decreases due to premature detection before signals settle
Solution Approach 1:
The sense amplifier operates in periodic cycles: during the precharge phase, bitlines are charged and wordlines are activated to allow data signals to settle; during the detection phase, the sense amplifier is enabled to detect settled signals. This periodic operation replaces continuous operation, reducing power consumption while ensuring accurate detection only when signals have stabilized.
Solution Approach 2:
Before the sense amplifier detects data values, preliminary actions are performed: bitlines are precharged to a reference voltage level, and wordlines are activated to allow sufficient time for differential signals to settle and stabilize. This preliminary preparation ensures that when detection occurs, signals are ready and stable, improving accuracy without requiring continuous operation.
2Reliability
If sense amplifiers continuously monitor bitlines, then detection capability is maintained, but power is wasted due to constant current sourcing to all sense amplifiers
Solution Approach 1:
Instead of continuous current sourcing to all sense amplifiers, current is supplied periodically only to active sense amplifiers during detection phases. The control logic enables current sources selectively based on which memory cells are being accessed, eliminating wasted power in inactive amplifiers while maintaining detection capability when needed.
Solution Approach 2:
The sense amplifier system transitions from a static continuous operation mode to a dynamic selective operation mode. Current sources and sense amplifier enablement are dynamically controlled based on read operation requirements, allowing the system to adapt power consumption to actual detection needs rather than maintaining constant power delivery to all amplifiers.
3Speed
If sense amplifiers detect signals immediately after wordline activation, then detection speed is maximized, but errors occur due to premature detection before differential signals settle
Solution Approach 1:
The system performs preliminary actions (bitline precharging and wordline activation) before enabling sense amplifier detection. This preliminary phase allows differential signals to settle to stable voltage levels, ensuring accurate detection. The timing is optimized so that the brief preliminary delay does not significantly impact overall read speed while dramatically improving detection accuracy.
Solution Approach 2:
The control logic acts as an intermediary that coordinates the timing between wordline activation and sense amplifier enablement. It introduces an optimized delay period that allows signals to settle while minimizing the overall read time, balancing speed and accuracy requirements through precise timing control.
Data Source
AI summary
Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a programmable logic device (PLD) includes a plurality of static random access memory (SRAM) cells adapted to configure the PLD for an intended use. A pair of bitlines are connected to the SRAM cells. At least one of the SRAM cells is adapted to provide data signals to the bitlines in response to a wordline signal received by the one of the SRAM cells during a read operation. A sense amplifier is connected to the bitlines and adapted to detect a data value from the data signals in response to a trigger signal received by the sense amplifier during the read operation. Logic is adapted to delay the trigger signal relative to the wordline signal to permit the data signals to settle before the sense amplifier detects the data value.