Programmable SRAM Source Bias Scheme for Leakage Reduction

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Solution Overview

Problem

Conventional power supply systems for SRAMs consume excessive power due to high voltage differences, leading to significant leakage currents, especially in standby modes, which is a concern for battery-powered large memory arrays.

Innovation Solution

A programmable source bias scheme that generates a second set of voltages with reduced high voltage and increased low voltage offsets using diode circuits and fuse elements or control signals, allowing selective application based on operational modes to minimize leakage currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If conventional power supply systems apply high voltage differences to SRAMs, then the memory can operate in active modes, but excessive power is consumed and significant leakage currents occur in standby modes

Engineering Contradiction:
Improveoperational powerVSAvoidleakage current
Core Design Contradiction:
PowerVSLoss of energy

Solution Approach 1:

The patent implements dynamic voltage adjustment by switching between a first power supply set (VDDH1, VSS1) for active modes and a second power supply set (VDDH2, VSS2) with reduced voltage differences for standby modes. The voltage levels are dynamically changed based on operational requirements, allowing the system to minimize leakage current during standby while maintaining full performance during active operation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameters of the power supply sets based on operational mode. The first power supply set provides higher voltage differences for active read/write operations, while the second power supply set provides reduced voltage differences for standby modes, directly addressing the leakage current problem by modifying the electrical parameters according to operational needs.

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If voltage offsets are reduced to minimize leakage currents, then power consumption decreases, but the ability to maintain proper voltage levels for active operation is compromised

Engineering Contradiction:
Improvepower consumptionVSAvoidvoltage level stability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent segments the power supply system into two distinct power supply sets: a first power supply set optimized for active operation with higher voltage levels, and a second power supply set optimized for standby mode with reduced voltage differences. This segmentation allows each subset to be independently optimized for its specific operational requirement without compromising the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically switches between the first and second power supply sets based on operational mode. During active read/write operations, the first power supply set is used to ensure proper voltage levels for reliable operation. During standby modes, the second power supply set is activated to reduce power consumption and leakage current, thus maintaining voltage level stability appropriate for each operational state.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces power consumption and leakage currents in SRAMs by applying lower voltage differences during standby modes, thereby extending battery life and reducing power loss in large memory arrays.

Implementation Method 1

A programmable source bias scheme that generates a second set of voltages with reduced high voltage and increased low voltage offsets using diode circuits

Methodology Applied
Scientific EffectDiode voltage drop: Diode

Data Source

PatentUS7688669B2Programmable SRAM source bias scheme for use with switchable SRAM power supply sets of voltages
Publication Date: 2010.03.30 STMICROELECTRONICS FRANCE
  • US7688669B2 patent drawing
  • US7688669B2 patent drawing
  • US7688669B2 patent drawing

AI summary

A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.