SRAM Subarray IO Block Architecture for Bit Line Length Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
SRAM memory devices, particularly in L1 caches, face performance degradation due to long bit lines that increase resistance and access time, and existing solutions to shorten bit lines either introduce additional delays or increase area requirements.
Innovation Solution
A 'Folded Architecture' is employed, dividing the memory cell array into subarrays with bit lines directly connected to a centrally located IO block, eliminating the need for global bit lines and reducing bit line length, thereby improving access speed while minimizing CPU area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit lines are made long to connect all memory cells to the IO block, then memory capacity can be increased, but access time increases and performance degrades
Solution Approach 1:
The memory cell array is divided into multiple subarrays, each with its own local IO block. This segmentation allows bit lines to be shorter within each subarray while maintaining overall large memory capacity. The local IO blocks can operate independently or in parallel, reducing the critical path delay and improving access time.
Solution Approach 2:
The patent introduces a hierarchical IO block structure with local, intermediate, and global levels, adding a spatial dimension to the IO organization. This multi-level hierarchy allows data to be accessed at different granularities - local subarrays can be accessed quickly through local IO blocks, while maintaining the ability to access larger regions through intermediate and global IO blocks.
2Loss of time
If bit lines are shortened to improve access speed, then memory capacity must be reduced
Solution Approach 1:
Multiple local IO blocks are merged into intermediate IO blocks, which are in turn merged into global IO blocks. This merging strategy allows the system to function as multiple small fast memory units while presenting a unified large-capacity interface to the CPU, effectively combining the benefits of short bit lines with large memory capacity.
Solution Approach 2:
The IO blocks are designed to serve multiple functions: local IO blocks handle fast access to their associated subarrays, intermediate IO blocks aggregate data from multiple local blocks, and global IO blocks provide the external interface. This multi-functionality allows the same basic IO block structure to operate at different levels of the memory hierarchy.
3Loss of time
If additional IO blocks are added to shorten bit lines, then CPU area increases
Solution Approach 1:
The IO block structure is organized hierarchically with local IO blocks nested within regions served by intermediate IO blocks, which are nested within regions served by global IO blocks. This nesting allows shared resources and reduces redundancy, as higher-level IO blocks can serve multiple lower-level blocks, reducing the total area required compared to having fully independent IO blocks for each subarray.
Data Source
AI summary
A memory device includes an array of memory cells that has a first sub array and a second sub array. A plurality of bit lines are connected to the memory cells, and an IO block is situated between the first sub array and the second sub array. The bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block. The IO block further includes data input and output terminals configured to receive data to be written to the array of memory cells and output data read from the array of memory cells via the plurality of bit lines