SRAM Access Timing Control for Bit-Line Precharge Margin
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Solution Overview
Problem
Existing pseudo two-port static random access memory (SRAM) technologies face challenges in ensuring a sufficient time margin between consecutive memory access operations, leading to inefficiencies and potential reliability issues due to large RC loading in conductive wires affecting bit-line precharge signals.
Innovation Solution
The implementation of a memory device with a memory control circuit that generates a delayed reset signal using an OR gate to manage the timing of memory access operations, ensuring a time margin between consecutive operations by delaying the start of the second operation until bit lines are fully precharged.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-port SRAM macro is used to achieve pseudo two-port functionality, then device complexity is reduced, but the time margin between consecutive memory access operations deteriorates due to large RC loading in conductive wires
Solution Approach 1:
The patent applies preliminary action by asserting the bit-line precharge signal before the memory access operation begins, ensuring that the bit lines are fully precharged to the predetermined voltage level in advance. This precharging action occurs during the time margin period between consecutive memory access operations, so that when the next operation starts, the bit lines are already ready, eliminating delays during the actual access operation.
Solution Approach 2:
The patent introduces a delay element as an intermediary component between the memory access operation completion signal and the start of the next operation. This delay element generates a time margin signal that extends the time margin period, allowing sufficient time for bit-line precharging despite the large RC loading in the conductive wires of the single-port SRAM macro.
2Productivity
If bit-line precharge is performed quickly, then productivity is improved, but reliability deteriorates due to insufficient time margin for complete precharging
Solution Approach 1:
The patent performs bit-line precharging in advance during the time margin period between operations, rather than attempting to precharge during the access operation itself. This preliminary precharging action ensures that by the time the memory access operation begins, the bit lines are already fully charged to the required voltage level, providing both speed and reliability.
Solution Approach 2:
The patent employs feedback by monitoring the bit-line voltage level and using this information to control the precharge signal duration. The time margin signal is generated based on feedback from the bit-line precharge status, ensuring that the precharge operation continues until the bit lines reach the predetermined voltage level, thereby guaranteeing reliability while optimizing the time margin.
Data Source
AI summary
The present disclosure provides a memory device, which includes a first memory array, and a memory control circuit. The memory control circuit performs a first memory access operation in response to a first clock pulse of a control internal clock signal. The memory control circuit generates a first reset signal and asserts a first bit-line precharge signal in response to completion of the first memory access operation, and generates a second reset signal using the first reset signal and a second bit-line precharge signal obtained from the first bit-line precharge signal. The memory control circuit generates a second clock pulse of the control internal clock in response to the second reset signal, and performs a second memory access operation associated with the second memory access command at the second clock pulse.