SRAM Unit With Trench Capacitor For Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current static random access memory (SRAM) units face challenges in achieving higher integration levels and reduced area occupation due to suboptimal memory cell array disposition and larger memory cell sizes.
Innovation Solution
The SRAM unit design includes a substrate with trenches, a gate dielectric layer, trench capacitors, source/drain regions, and contacts, with a passing gate above the trench capacitor, and a capacitor structure comprising a lower electrode, dielectric layer, and upper electrode, optimized with shallow trench isolation and oxide/nitride/oxide composite stack layers, to enhance integration and reduce area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional SRAM memory cells (6T or 4T2R) are used, then fast data processing speed and simplicity of fabrication are achieved, but area occupation is large (10 to 16 times that of DRAM memory cell)
Solution Approach 1:
The patent merges the advantages of SRAM (fast access speed, simple fabrication) and DRAM (small area) by creating a hybrid memory cell that uses SRAM transistor structure with DRAM-like area efficiency through optimized layout and shared components
Solution Approach 2:
The patent transitions from planar layout to three-dimensional structure by forming trench capacitors vertically in the substrate, utilizing the vertical dimension to reduce planar area occupation while maintaining functionality
2Area of stationary object
If DRAM memory cells (1T1C) are used, then area occupation is reduced, but fabrication complexity increases due to capacitor fabrication requirements
Solution Approach 1:
The patent extracts the capacitor structure from the conventional DRAM implementation and integrates it as a trench capacitor formed within the substrate, separating the capacitor formation process from the transistor fabrication process to simplify overall manufacturing
Solution Approach 2:
The trench capacitor structure serves multiple functions: it provides the storage function of a DRAM capacitor while being formed using standard semiconductor fabrication processes compatible with CMOS technology, thus eliminating the need for specialized capacitor fabrication equipment and processes
3Area of stationary object
If 1T-SRAM memory cells are used, then area occupation is reduced and integration level is improved, but memory unit disposition is not optimal resulting in lower integration level
Solution Approach 1:
The patent employs asymmetric layout where the trench capacitor is positioned offset from the center of the memory cell, allowing optimized spacing and sharing of components between adjacent cells, thereby improving overall array integration density
Solution Approach 2:
The patent segments the memory cell into distinct functional regions with the trench capacitor positioned in a dedicated region, allowing independent optimization of transistor and capacitor layouts and facilitating better packing density in the memory array
Data Source
AI summary
A static random access memory (SRAM) unit comprising a substrate, a gate dielectric layer, a gate, a trench capacitor, a pair of source/drain regions, a first contact and a second contact is provided. The substrate has a trench formed therein. The gate dielectric layer is disposed on the substrate and the gate is disposed on the gate dielectric layer. The trench capacitor is disposed in the trench near one side of the gate. The source/drain regions are disposed in the substrate near the respective sides of the gate with one of the source/drain region positioned between the gate and the trench capacitor. The first contact is electrically connected to the trench capacitor and the second contact is electrically connected to the other source/drain region.