SRAM Bit Line Charge Sharing Precharge at Vdd/2
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Solution Overview
Problem
The reduced bit line pitch in SRAMs prevents the implementation of sense amplifiers, leading to substantial power consumption during read and write operations due to full precharge voltage, which is inefficient and may cause static noise margin issues.
Innovation Solution
A bit line charge sharing precharge circuit that precharges bit lines to half the memory power supply voltage, sharing charge between bit lines through a transmission gate and additional capacitance, boosting the precharge voltage if necessary, to reduce power consumption while maintaining sufficient static noise margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bit line pitch is reduced to accommodate smaller transistor sizes, then transistor density increases, but sense amplifiers cannot be implemented within the bit line pitch
Solution Approach 1:
The patent extracts the precharge function from the traditional sense amplifier circuit and implements it separately using dedicated precharge circuits that couple bit lines to a precharge voltage. This separation allows sense amplifier functionality to be eliminated while maintaining bit line precharge capability, thereby enabling reduced bit line pitch without requiring sense amplifiers within the pitch constraint.
2Reliability
If full precharge voltage is applied to bit lines during read and write operations, then bit lines are fully prepared for operation, but power consumption increases substantially
Solution Approach 1:
The patent applies partial precharge action by charging bit lines to an intermediate voltage level (Vdd/2) rather than the full precharge voltage (Vdd) during certain operations. This partial precharge is sufficient for non-selected bit lines and significantly reduces power consumption while maintaining operational reliability. The circuit includes precharge circuits that can selectively apply different voltage levels based on operation type.
Solution Approach 2:
The patent changes the precharge voltage parameter from the traditional full voltage (Vdd) to an intermediate voltage (Vdd/2) for non-selected bit lines during read and write operations. This parameter change is controlled by operation type signals that selectively enable different precharge circuits, thereby reducing power consumption while maintaining sufficient signal margins for successful operations.
3Reliability
If full precharge voltage is used during operations, then noise margin is maintained, but power consumption becomes inefficient
Solution Approach 1:
The patent applies different precharge voltage qualities to different bit lines based on their selection status. Selected bit lines receive full precharge voltage (Vdd) to maintain maximum noise margin, while non-selected bit lines receive intermediate voltage (Vdd/2) to reduce power consumption. This local differentiation is achieved through operation type signals that selectively control precharge circuit activation, thereby optimizing the balance between noise margin and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Substantial power savings are achieved with maintained static noise margin by precharging bit lines to half the memory power supply voltage, reducing the need for separate power supply voltages and minimizing power consumption during read and write operations.
Implementation Method 1
coupling a bit line to a complement bit line during a charge sharing period following the completion of the first precharge period
Implementation Method 2
a precharge node; a second switch coupled between the precharge node and the power supply node
Data Source
AI summary
A bit line charge sharing precharge circuit is provided that precharges a bit line pair during a charge sharing period in which the bit line pair is isolated from a memory power supply voltage. Prior to the charge sharing period, one of the bit lines in the bit line pair was charged to the memory power supply voltage whereas a remaining one was either fully or partially discharged. Charge thus flows from the charged bit line to the discharge bit line during the charge sharing period to precharge the bit lines for a current read or write operation.