SRAM Subarray Work Function Stacks for Speed-Power Balance
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Solution Overview
Problem
Conventional SRAM memory devices struggle to balance speed and power consumption due to transistors having similar structure and work function layer arrangements, making it difficult to achieve optimal performance.
Innovation Solution
Implementing an SRAM array with modularized work function arrangements for FinFETs and MBC transistors, where each subarray consists of transistors with similar dimensions but different work function stacks to achieve varying threshold voltages, balancing speed and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If all transistors in an SRAM array have similar structure and work function layer arrangement, then manufacturing is simplified, but it becomes difficult to balance speed and power consumption
Solution Approach 1:
The patent applies local quality by introducing different work function layer arrangements in specific regions of the SRAM array. First subarrays have transistors with a first work function layer arrangement optimized for speed, while second subarrays have transistors with a second work function layer arrangement optimized for low power consumption. This allows different parts of the array to have specialized characteristics without requiring complete structural redesign of all transistors.
Solution Approach 2:
The SRAM array is segmented into first subarrays and second subarrays with different transistor configurations. Each subarray can be independently optimized for specific performance characteristics (speed or power consumption) while maintaining overall array functionality. This segmentation enables performance optimization without compromising manufacturing simplicity across the entire array.
2Productivity
If transistors are scaled down to increase functional density, then production efficiency increases and costs decrease, but achieving balance between speed and power consumption becomes more difficult
Solution Approach 1:
Within the scaled-down high-density SRAM array, the patent implements local quality by creating regions with different work function layer arrangements. This allows specific subarrays to be optimized for speed or power consumption even as overall transistor dimensions are reduced, maintaining performance optimization capability despite scaling challenges.
Solution Approach 2:
The patent changes the work function parameter of transistors by using different work function layer arrangements in different subarrays. This parameter variation enables optimization of threshold voltages and performance characteristics without changing the fundamental scaled-down transistor structure, thus maintaining high functional density while achieving performance differentiation.
Data Source
AI summary
Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.