SRAM Write Assist Circuit Using Bit Line Driven Charge Pump
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Solution Overview
Problem
Existing SRAM write operation assist circuits rely on external driving signals with strict timing requirements, making them challenging to design and stabilize due to random doping fluctuations and process parameter changes.
Innovation Solution
A write operation assist circuit that does not rely on an external driving signal, utilizing a pre-charging circuit, drive signal circuit, programmable delay circuit, charge pump, write driving circuit, and column selector, where the charge pump is driven by the bit lines, eliminating the need for external drive signals and strict timing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external driving signals are used to drive the charge pump, then the write operation can be performed, but the timing requirements become strict and the design stability deteriorates due to random doping fluctuations
Solution Approach 1:
The charge pump is driven by the bit lines themselves rather than external driving signals. The bit lines generate the driving voltage through their own signal transitions, eliminating the need for separate external drive circuits and reducing timing constraints while improving write operation stability
2Ease of operation
If external driving signals with strict timing requirements are used, then the charge pump can be driven, but the sensitivity to timing requirements increases and design becomes more challenging
Solution Approach 1:
The external driving signal source is extracted and removed from the system. The charge pump is redesigned to be driven internally by the bit lines through their natural signal transitions, eliminating the need for external drive signals and their associated timing constraints
Data Source
AI summary
A write operation assist circuit is provided, including: pre-charging circuit, a drive signal circuit, a programmable delay circuit, a charge pump, a write driving circuit and a column selector, wherein the pre-charging circuit has a pre-charging signal output terminal coupled to a pre-charging signal input terminal of the drive signal circuit, a first voltage output terminal coupled to a first bit line, and a second voltage output terminal coupled to a second bit line; the driving signal circuit has a first input terminal coupled to the first bit line, a second input terminal coupled to the second bit line, a first output terminal coupled to a first input terminal of the programmable delay circuit, and a second output terminal coupled to a second input terminal of the programmable delay circuit; the programmable delay circuit has an output terminal coupled to a first terminal of the charge pump.