SRAM Write Assist Circuit with Invariant Boost Voltage
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Solution Overview
Problem
As integrated circuits are scaled down, the compromise between read and write functions in SRAM cells becomes more challenging due to reduced read and write margins, leading to errors in operations, and existing write assist circuits face difficulties in maintaining a consistent boost voltage across process, voltage, and temperature variations.
Innovation Solution
A write assist circuit with a boost capacitor and a controlled current source, coupled with a FET diode stack, provides a near constant boost voltage by charging and discharging the capacitor in a controlled manner, independent of the power supply level, using a digital to analog converter for creating a reference current source and tuning the boost magnitude.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the transistors in the cross-coupled latch are made weaker to enable over-driving during write operations, then write performance is improved, but the ability to maintain data value during read operations deteriorates
Solution Approach 1:
The patent separates the write and read functions by introducing dedicated write assist circuitry (boost capacitors, write assist transistors) that operates only during write operations. This allows the main cross-coupled latch transistors to be optimized for read stability while the assist circuit provides the additional drive strength needed for writes, effectively segmenting the functionality between core latch and assist circuitry.
Solution Approach 2:
The boost capacitors are pre-charged to a specific voltage level before write operations begin. When a write operation is initiated, these pre-charged capacitors immediately provide the necessary voltage boost to overdrive the latch transistors, eliminating the need to make the latch transistors inherently weaker and allowing them to maintain their optimal strength for both read and write operations.
2Productivity
If access transistors are optimized for write operations by reducing on-resistance, then write performance improves, but cell isolation during read operations deteriorates
Solution Approach 1:
The patent employs dynamically controllable access transistors whose on-resistance can be adjusted based on the operation type. During write operations, the access transistors are configured with lower on-resistance to enable fast data insertion. During read operations, they are configured with higher on-resistance to isolate the cell from bit line capacitance, preventing cell disturbance. This dynamic adjustment resolves the contradiction between write speed and read isolation.
3Area of stationary object
If SRAM cells are scaled down to reduce circuit size, then area is reduced, but read and write margins deteriorate
Solution Approach 1:
The patent introduces boost capacitors and write assist transistors as intermediary elements between the write driver and the cross-coupled latch. These intermediaries provide the additional voltage boost needed to overcome the reduced margins caused by scaling, allowing the cell dimensions to be reduced while maintaining adequate write and read margins through the assist circuitry.
4Productivity
If existing write assist circuits are used to provide voltage boost, then write performance improves, but consistency of boost voltage across process, voltage, and temperature variations deteriorates
Solution Approach 1:
The patent incorporates feedback mechanisms through carefully designed bias circuits and voltage references that monitor and adjust the boost voltage level. The write assist circuitry includes reference voltages and control logic that compensate for process, voltage, and temperature variations, ensuring that the boost voltage remains consistent and effective across different operating conditions. This feedback control resolves the issue of boost voltage inconsistency in existing designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures reliable write assist with reduced power consumption and circuit complexity, maintaining a consistent boost voltage across various process, voltage, and temperature conditions, meeting 5.8 sigma writeability targets and reducing variability.
Implementation Method 1
a boost capacitor with a first node coupled to a bitline through control logic and a second node connected to a field effect transistor (FET) diode stack
Implementation Method 2
a plurality of boost enabled transistors which each contain a gate connected to a boost control signal, and a controlled current source coupled between a ground signal and the second node of the boost capacitor
Data Source
AI summary
Approaches for a write assist circuit are provided. The write assist circuit includes a boost capacitor with a first node coupled to a bitline through control logic and a second node connected to a field effect transistor (FET) diode stack, a plurality of boot enabled transistors which each contain a gate connected to a boost control signal, and a controlled current source coupled between a ground signal and the second node of the boost capacitor. In the write assist circuit, the boost capacitor has a discharge path which is controlled to provide a boost voltage which is invariant to a level of a power supply signal.