SRAM Write-Assist Voltage Generation for Leakage Reduction
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Solution Overview
Problem
The scaling down of transistor feature sizes in static random access memory (SRAM) devices leads to increased leakage current, resulting in unacceptable power consumption and functional failures, while attempts to minimize leakage negatively impact writeability, and existing methods to address write margin issues either slow down write access or increase power consumption.
Innovation Solution
The implementation of a local power supply voltage node and a generator circuit to generate a power supply voltage that is either equal to or less than the global power supply voltage, which increases write margin during write operations and reduces current leakage during power-down operations by adjusting the voltage levels accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the operating voltage of the SRAM cell is raised to compensate for reduced writeability, then write margin is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by introducing a local power supply voltage node that can be independently controlled from the global power supply. This allows different voltage levels to be applied to different parts of the SRAM cell - specifically, a reduced voltage is applied to the bit line during write operations, which improves write margin without requiring the entire cell to operate at higher voltage, thus avoiding the power consumption penalty
Solution Approach 2:
The patent changes the voltage parameter dynamically by introducing a reduced voltage level (VDD/2) for the bit line during write operations. This parameter change allows the write operation to proceed with improved margin while the rest of the cell continues to operate at the normal voltage level, thereby maintaining acceptable power consumption levels
2Reliability
If the write access speed is slowed down to improve write margin, then write reliability is improved, but overall speed decreases
Solution Approach 1:
The patent changes the voltage parameter applied to the bit line during write operations, using a reduced voltage level that improves write margin without requiring extended write time. This parameter change enables fast write operations to proceed with adequate margin, thus improving reliability without sacrificing speed
3Reliability
If the size of the SRAM cell is increased to raise local ground voltage, then write margin is improved, but silicon area increases
Solution Approach 1:
The patent applies local quality by introducing a local power supply voltage node that can be independently controlled from the global power supply. This allows different voltage levels to be applied to different parts of the SRAM cell - specifically, a reduced voltage is applied to the bit line during write operations, which improves write margin without requiring the entire cell to be enlarged
Solution Approach 2:
The patent introduces an intermediary element - the local power supply voltage node - that mediates between the global power supply and the bit line. This intermediary allows for independent voltage control of the bit line, enabling improved write margin through voltage adjustment rather than through increasing cell size
Data Source
AI summary
Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by a power supply voltage generator circuit, the generated power supply voltage being substantially equal to or less than a global power supply voltage provided to one or more transistors of the SRAM cell during a write-enable or power-down mode.