Spread Spectrum Clock Generator Using Variable Delay Elements
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Solution Overview
Problem
Existing spread spectrum clock generators, particularly those using phase locked loops, are costly and reduce microprocessor throughput due to frequency dithering, which limits the maximum clock frequency and processing performance.
Innovation Solution
A programmable spread spectrum clock generator that uses a variable delay element, controlled by a programmable register and non-linear signal generator, to smoothly vary the frequency of the clock signal without discrete delays or phase locked loops, thereby reducing electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a phase locked loop (PLL) spread spectrum clock generator is used, then electromagnetic interference peak levels are reduced, but the device cost increases due to large and costly loop filter capacitors
Solution Approach 1:
The patent removes the PLL and loop filter capacitor from the spread spectrum clock generator circuit. Instead of using a PLL-based approach that requires large external capacitors, the invention implements spread spectrum functionality directly within the clock generator using a variable delay line controlled by a dither signal, eliminating the need for costly external components while maintaining EMI reduction effectiveness
Solution Approach 2:
The patent creates a simplified copy of the spread spectrum function that achieves the same EMI reduction effect without requiring the complex PLL infrastructure. The variable delay line with dither control replicates the frequency spreading effect of a PLL system but with significantly reduced component requirements and lower cost
2Object-affected harmful factors
If the clock signal frequency is dithered between maximum frequency and a lesser frequency for spread spectrum clocking, then EMI peak levels are reduced, but the average clock frequency decreases, reducing microprocessor throughput
Solution Approach 1:
The patent implements a dynamic delay adjustment mechanism where the delay line is controlled by a dither signal that continuously varies the propagation delay. This dynamic control allows the system to achieve frequency spreading for EMI reduction while maintaining the ability to operate at or near the maximum clock frequency, thereby preserving microprocessor throughput
Solution Approach 2:
The patent changes the approach from varying the clock frequency itself to varying the propagation delay parameter of the clock signal path. By adjusting the delay rather than the frequency, the system achieves spread spectrum effects without forcing the microprocessor to operate at reduced frequencies, thus maintaining maximum processing throughput
3Object-affected harmful factors
If discrete delayed clock signals are used for spread spectrum generation, then EMI is reduced, but the frequency bandwidth spreading is limited by discrete delay steps
Solution Approach 1:
The patent replaces discrete, fixed delay lines with a continuous, dynamically controllable variable delay line. This allows the delay amount to be adjusted continuously rather than in discrete steps, providing fine-grained control over the frequency spreading characteristic and enabling more precise and effective EMI reduction across a broader frequency range
Solution Approach 2:
The patent pre-establishes a variable delay mechanism that can be continuously adjusted to achieve the desired frequency spreading effect. By having the delay capability prepared and continuously可调 in advance, the system can respond dynamically to different operating conditions and achieve optimal EMI reduction without being constrained by fixed discrete delay values
Data Source
AI summary
A programmable spread spectrum clock generator (SSCG) reduces electromagnetic interference by spreading the frequency bandwidth of an output signal. The rate at which the frequency of the output signal changes, as well as other aspects of the output signal, are software programmable. The programmable SSCG receives a periodic signal whose cycles have substantially identical periods and outputs the output signal whose cycles have periods that vary smoothly over a plurality of cycles of the periodic signal. The programmable SSCG generates a control signal using the periodic signal. The programmable SSCG includes a variable delay element that generates the output signal by delaying the periods of the periodic signal based on the magnitude of the control signal. The output signal is generated without using a phase locked loop. Moreover, successive cycles of the output signal rarely have identical periods.