SSD Garbage Collection Buffering for Incremental NAND Writes
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Solution Overview
Problem
The large amount of assembled valid user data stored in low-cost, slower DRAM during garbage collection in SSDs reduces performance due to increased power consumption and reduced efficiency in transferring data to faster SRAM.
Innovation Solution
Transfer and write data to non-volatile memory in smaller chunks, using thresholds to manage data size in buffers, allowing early release of buffers for reuse and reducing the need for external memory storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large amount of valid user data is assembled and stored in DRAM during garbage collection, then the garbage collection throughput is improved, but the power consumption increases and the performance is reduced due to slower DRAM access compared to SRAM
Solution Approach 1:
The patent segments the large amount of valid user data into smaller chunks and transfers them incrementally from DRAM to NAND flash during garbage collection. Instead of assembling and holding all data in DRAM simultaneously, the controller divides the data transfer into multiple smaller operations, reducing the amount of data that needs to be held in external memory at any one time and thereby reducing power consumption while maintaining garbage collection throughput.
2Manufacturing precision
If a large amount of valid user data is assembled in DRAM, then the data can be programmed in full sequence program mode, but the time required to assemble and transfer the data increases
Solution Approach 1:
The patent applies preliminary action by initiating data transfer from DRAM to NAND flash before the DRAM buffer is completely filled. The controller monitors the amount of valid data in the DRAM buffer and starts transferring chunks of data to the NAND flash in advance, allowing the buffer to be emptied and reused sooner. This overlapping of operations reduces the total time required for data assembly and transfer while still enabling full sequence program mode to be used when sufficient data is available.
3Ease of manufacture
If DRAM is used to store assembled valid user data, then the cost is reduced compared to using SRAM, but the garbage collection performance is reduced due to slower access speed
Solution Approach 1:
The patent segments the data transfer operation into smaller chunks that can be transferred incrementally from DRAM to NAND flash. This segmentation allows the system to use cost-effective DRAM for buffering while maintaining good performance by avoiding the need to hold large amounts of data in slow external memory simultaneously. The incremental transfer approach reduces the bottleneck effect of DRAM's slower access speed compared to SRAM.
Data Source
AI summary
A system may include a controller, a non-volatile memory (NVM) array including an NVM and a program buffer, and a buffer for garbage collection. The controller may read valid data from a superblock and store the valid data to the buffer; in response to storing the valid data to the buffer, determine that a size of data stored in the buffer is greater than or equal to a first threshold and less than an amount of data for being written in a program mode, and write the data stored in the buffer, to the program buffer; determine that the size of data is greater than or equal to the amount of data, and program the data stored in the program buffer to the NVM; and in response to completion of writing the data stored in the buffer to the first program buffer, empty the buffer.