SSD Open-Block Read Bias for Last-Wordline Latency
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Solution Overview
Problem
Solid-state drives (SSDs) face challenges in reducing read latency in last-written wordlines of open blocks due to increased string current (Icell) and read errors, which can trigger read-recovery schemes, leading to significant latency issues.
Innovation Solution
Implementing a reduced bitline (BL) bias to compensate for the increased Icell in last-written wordlines, lowering the BL bias by 5-15% relative to normal biases based on factors like temperature, P/E cycles, and block programming, to improve read accuracy and reduce read errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If normal BL bias is used to read the last-written WL of an open block, then read operation can be performed with standard voltage, but increased Icell causes threshold voltage shift leading to read errors and activation of read-recovery schemes
Solution Approach 1:
The patent changes the BL bias voltage parameter specifically for reading the last-written wordline of open blocks. By reducing the BL bias voltage by 5-15% compared to normal read operations, the patent compensates for the increased string current (Icell) effect that occurs in partially programmed blocks, thereby preventing threshold voltage shifts and read errors without activating read-recovery schemes.
Solution Approach 2:
The patent applies a localized solution by implementing different BL bias voltage levels for different wordline types. Specifically, the reduced BL bias is applied only to the last-written wordline of open blocks, while normal BL bias is maintained for fully programmed blocks and other wordlines. This targeted approach resolves the read accuracy issue in specific problematic cases without affecting overall system performance.
2Reliability
If reduced BL bias is applied to compensate for increased Icell in last-written WL, then read errors are reduced and read-recovery scheme activations decrease, but additional voltage control complexity is introduced
Solution Approach 1:
The patent implements preliminary action by pre-determining which wordlines require reduced BL bias based on block programming status. The controller identifies open blocks and their last-written wordlines in advance, preparing the appropriate voltage level before the read operation begins. This proactive approach prevents read errors before they occur rather than requiring complex post-read correction mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces read errors and read-recovery scheme activations, thereby improving read latency in last-written wordlines of open blocks in SSDs.
Implementation Method 1
reading the last-written WL with a reduced BL bias which raises a Vt to compensate for an increase in Icell
Data Source
AI summary
A solid-state drive with improved read latency in a last-written wordline of an open, or partially programmed, block, and a method of improving read latency in a last-written wordline of an open block in a solid-state drive. The solid-state drive includes a NAND-based or other non-volatile memory media. The media includes the open, or partially programmed, block, and a controller. The controller receives a read request that includes the last-written wordline of the open block. The controller performs a read operation to fulfill the read request, including reading the last-written wordline with a reduced bitline bias, which raises a threshold voltage to compensate for an increase in string current. The reduced bitline bias is lower than a normal bitline bias used to read a non-last-written wordline.