SSD Tester Failure Detection with Interleaved Buffer Memory

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Solution Overview

Problem

Existing SSD testers face challenges in real-time failure detection due to the inability to compare readout data with expectation data stored in a single buffer memory, leading to increased time in determining pass or failure, as data can only be read out after the operation is stopped.

Innovation Solution

Implementing a failure detection apparatus with multiple buffer memories that store readout data in an interleaving manner, allowing continuous comparison of test patterns with readout data, and utilizing a multiplexer to select and output data from these buffers for real-time processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a single buffer memory is used to store readout data, then the device complexity is reduced, but the testing speed decreases and real-time failure detection cannot be achieved

Engineering Contradiction:
Improvetesting speedVSAvoidmemory system complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The single buffer memory is segmented into multiple buffer memories (first buffer memory and second buffer memory) that operate in an interleaved manner. While one buffer is being written to, the other can be read from, enabling continuous data flow and real-time comparison without waiting for buffer operations to complete, thus maintaining high testing speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interleaved operation of multiple buffers ensures continuous useful action by eliminating idle time. While the first buffer is being written with readout data, the second buffer simultaneously provides data for comparison, and vice versa. This continuous operation enables real-time failure detection without interruption.

Inventive Principle:
Principle #20Continuity of useful action

2Loss of time

If readout data is stored in a buffer before comparison, then data integrity is ensured, but the time required to determine pass or failure increases

Engineering Contradiction:
Improvetime to determine pass or failureVSAvoiddata comparison accuracy
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

Readout data is preliminarily stored in interleaved buffers before comparison with expectation data. The buffers are prepared and filled in advance during the writing operation, so when comparison is needed, the data is already organized and ready, minimizing the time required for the actual comparison while ensuring data integrity through the buffer structure.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The buffer memories serve as intermediaries between the readout data source and the comparison operation. They temporarily hold the data in an organized manner, allowing the comparison unit to access ready-to-compare data without directly interfacing with the data source, thus speeding up the determination process while maintaining reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If multiple buffer memories are used for interleaved storage, then real-time comparison is enabled, but the device complexity increases

Engineering Contradiction:
Improvetesting throughputVSAvoidbuffer memory system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Multiple buffer memories are merged into a unified interleaved buffer system that is controlled by a single control unit. The control unit manages the interleaved writing and reading operations across all buffers, presenting a simplified interface to the rest of the system. This merging approach enables real-time comparison and high productivity while managing complexity through centralized control.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9159454B2Failure detection apparatus for solid state drive tester
Publication Date: 2015.10.13 UNITEST INC
  • US9159454B2 patent drawing
  • US9159454B2 patent drawing
  • US9159454B2 patent drawing

AI summary

A failure detection apparatus for a solid state driver tester is provided. The failure detection apparatus includes a host terminal for receiving a test condition for testing a storage from a user and a test control unit for creating a test pattern according to the test condition or creating a test pattern at random, and adaptively selects an interface according to a type of the storage to be tested to test the storage with the test pattern. The test control unit includes a plurality of buffer memories for storing readout data of the storage, stores the readout data in the buffer memories in an interleaving manner, and endows comparison of the created test pattern and the readout data stored in the buffer memories with continuity to test the storage in real time.