Solid State Lighting Dies with Quantum Emitters
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Solution Overview
Problem
Conventional solid-state lighting (SSL) devices, such as LEDs, suffer from performance issues due to high densities of crystal defects like threading dislocations and indentation defects, which affect optical and electrical performance by causing current leakage and low optical efficiencies.
Innovation Solution
The formation of individual quantum emitters on the SSL structure, where the SSL structure is etched to create separated emitters with specific dimensions and configurations, reducing the impact of lattice dislocations and enhancing optical efficiencies by localizing their negative effects and allowing for controlled emission characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional epitaxial growth is used to form GaN layers, then the LED structure can be manufactured, but high density of threading dislocations and crystal defects occur which degrade optical and electrical performance
Solution Approach 1:
The patent divides the continuous GaN layer into discrete, spatially separated quantum emitter regions. By segmenting the active layer into isolated emitters, the threading dislocations are confined to specific regions rather than propagating throughout the entire layer, thereby reducing their cumulative harmful effect on device performance while maintaining structural manufacturability
Solution Approach 2:
The patent creates regions with different properties: the quantum emitter regions have optimized crystal quality and controlled dislocation density, while the surrounding areas can tolerate higher defect densities. This local differentiation allows the critical emission zones to maintain high performance while the overall structure remains manufacturable using conventional epitaxial growth
2Ease of manufacture
If the GaN layer is formed with threading dislocations, then the LED can be manufactured using conventional processes, but current leakage occurs reducing electrical efficiency
Solution Approach 1:
The continuous conductive path provided by threading dislocations is interrupted by segmenting the GaN layer into discrete quantum emitter regions. This segmentation breaks the current leakage pathways while maintaining electrical connectivity through the p-n junction, thereby reducing energy loss without requiring non-conventional manufacturing processes
3Ease of manufacture
If the GaN layer contains crystal defects, then conventional epitaxial growth can be used, but optical efficiency is reduced due to non-radiative recombination
Solution Approach 1:
The patent creates localized quantum emitter regions where high optical quality is achieved through controlled growth conditions, while surrounding areas can accommodate higher defect densities. This local quality differentiation ensures that photons are generated primarily in the high-quality emitter regions, maintaining high optical efficiency while using conventional epitaxial growth processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the density of lattice dislocations, localizes their impact, and improves optical efficiencies by allowing more light to escape and achieving a color shift through quantum confinement, resulting in higher performance SSL devices.
Implementation Method 1
achieving a color shift through quantum confinement
Data Source
AI summary
Solid state lighting dies and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting die includes a substrate material, a first semiconductor material, a second semiconductor material, and an active region between the first and second semiconductor materials. The second semiconductor material has a surface facing away from the substrate material. The solid state lighting die also includes a plurality of openings extending from the surface of the second semiconductor material toward the substrate material.