Static Timing Analysis Path Delay Accuracy via Connectivity Constraints
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Solution Overview
Problem
Traditional static timing analysis (STA) methods calculate path delay by summing maximum device delays, leading to pessimistic estimates that can incorrectly identify paths as violating timing requirements, resulting in unnecessary optimization efforts and increased costs.
Innovation Solution
The method involves determining connectivity between devices in a circuit path and generating delay constraints based on this connectivity to accurately calculate path delay, excluding device delay pairs that cannot occur simultaneously, thereby reducing pessimism in path delay calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional STA method sums maximum device delays of respective devices in the path, then the calculation is simple and fast, but the path delay estimate is pessimistic and inaccurate
Solution Approach 1:
The invention segments the path delay calculation by dividing it into individual device delay components, each analyzed separately for its connectivity conditions. This allows the system to identify which devices can simultaneously reach maximum delay based on their input pattern requirements, rather than blindly summing all maximum delays. The segmentation enables precise identification of delay-contributing devices while excluding those that cannot simultaneously operate at maximum delay.
Solution Approach 2:
The invention changes the parameter consideration from fixed maximum delay values to conditional delay values based on input patterns. By analyzing the input pattern requirements of each device and determining which patterns can coexist, the system dynamically adjusts which device delays are summed. This parameter change transforms the calculation from a static sum of maximums to a dynamic sum based on feasible input pattern combinations.
2Productivity
If STA assumes all devices reach maximum delay simultaneously, then the calculation is straightforward, but unnecessary optimization efforts are required increasing running time and wafer size
Solution Approach 1:
The invention performs preliminary analysis of device connectivity and input pattern requirements before conducting the full STA process. By pre-determining which devices can simultaneously reach maximum delay based on their connectivity and input pattern constraints, the system prepares an accurate set of delay components to sum. This preliminary action prevents the need for subsequent iterative optimizations that would be required if the initial calculation was pessimistic.
3Reliability
If maximum device delays are summed without considering connectivity, then the calculation is simple, but the accuracy of STA is reduced leading to false timing violations
Solution Approach 1:
The invention introduces connectivity analysis as an intermediary step between device identification and delay summation. This intermediary process examines the input pattern requirements of each device to determine whether their maximum delays can coexist. The connectivity analysis acts as a filter that identifies feasible delay combinations, ensuring that only devices capable of simultaneous maximum delay operation are included in the sum, thereby improving reliability without excessive complexity.
Data Source
AI summary
A method of for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.