Path-Based Static Timing Analysis Using Shared Segment Delay Estimation
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Solution Overview
Problem
The computational intensity of exhaustive path-based static timing analysis (STA) in integrated circuit design leads to increased runtime as the complexity of integrated circuits grows, making it impractical for large designs.
Innovation Solution
A method that estimates path-based delays by reusing previously computed timing information for shared segments, reducing the need for full recomputation by comparing estimated delays with thresholds, thereby identifying worst or best-case path-based delays without actual full path-based STA for each path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If exhaustive path-based STA is performed to achieve accurate timing analysis, then timing accuracy is improved, but computational runtime increases exponentially
Solution Approach 1:
The patent performs preliminary actions by computing path delays for a subset of paths and storing them in a data structure. When evaluating new paths, the system checks if paths share segments with previously computed paths, and if so, uses the stored timing information to estimate delays without performing full recomputation. This preliminary computation and caching of results enables faster subsequent analyses while maintaining accuracy.
Solution Approach 2:
The patent applies partial action by computing path-based STA only for paths that do not share segments with previously analyzed paths, rather than performing complete analysis on all paths. By using estimation techniques for paths with shared segments, the system reduces computational effort while maintaining sufficient timing accuracy for design verification.
2Measurement precision
If path-based STA is performed to provide less pessimistic timing estimates, then timing estimate accuracy is improved, but computational intensity increases
Solution Approach 1:
The patent merges previously computed path-based timing information with current path analysis by checking for shared segments between paths. When segments are shared, the system combines the stored timing data from previous computations with current path characteristics to estimate delays, thereby reducing redundant computations while maintaining accurate timing estimates.
Solution Approach 2:
The patent uses copying by creating a data structure that stores timing information for previously analyzed paths and segments. This copied information is then referenced and reused during subsequent path analyses, avoiding the need to recompute timing parameters for shared segments and reducing overall computational intensity.
3Productivity
If graph-based STA is used to achieve fast analysis, then computational speed is improved, but timing results become pessimistic
Solution Approach 1:
The patent segments the timing analysis process into two parts: fast graph-based STA for initial analysis and selective path-based STA for critical paths. By dividing the analysis workload, the system maintains the speed benefits of graph-based methods for overall timing estimation while applying more accurate path-based methods only where necessary to reduce pessimism in critical timing paths.
Data Source
AI summary
One embodiment of the present invention provides a system that performs an efficient path-based static timing analysis (STA) in a circuit design. During operation, the system identifies a set of paths within the circuit design, wherein each path includes one or more segments. For a path in the set of paths, the system determines if at least one segment in the path is shared with a different path which was previously computed by performing a path-based STA, wherein the at least one segment in the different path is associated with previously computed path-based timing information. If so, the system then performs an estimation of a path-based delay for the path based at least on the path-based timing information associated with the shared segment in the different path. Otherwise, the system computes a path-based delay for the path by performing a path-based STA on the path.