Stack Package Chip Selection via Delay-Time-Difference Sensing
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Solution Overview
Problem
Conventional stack packages with Through Silicon Vias (TSVs) face challenges in efficiently selecting specific chips due to the need for multiple chip-selection pads, leading to increased fabrication costs and complexity, as the same chip-selection pads are used across stacked chips, resulting in larger package sizes and management issues.
Innovation Solution
A stack package system that includes a chip selection controller with reference signal and control signal management, utilizing delay-time-difference sensing to generate and store chip selection information, allowing for the reduction of chip-selection pads without increasing package size by adjusting delay times and using TSVs to transmit signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple chip-selection pads are used to select specific chips in a stack package, then chip selection functionality is achieved, but the package size increases and fabrication costs increase
Solution Approach 1:
The patent combines multiple chip-selection pad functions into a single shared chip-selection pad. Instead of having separate selection pads for each chip layer, the invention uses one common pad that can selectively activate different chips through redistribution layers, thereby reducing the total number of pads and minimizing package size while maintaining full chip selection capability
Solution Approach 2:
The patent introduces redistribution layers (RDLs) as intermediary structures between the single chip-selection pad and multiple chips. These RDLs act as mediators that route the selection signal from the shared pad to specific chips based on their position in the stack, enabling indirect but precise chip selection without requiring dedicated pads for each chip
2Adaptability or versatility
If multiple chip-selection pads are allocated for each stacked chip, then each chip can be independently selected, but the number of pads increases leading to larger package size
Solution Approach 1:
The patent makes a single chip-selection pad universal by designing it to serve multiple chips simultaneously. Through the redistribution layer network, this one pad can be dynamically connected to any chip in the stack, allowing it to perform the selection function for all chips rather than each pad being dedicated to a single chip
Solution Approach 2:
The patent transitions from a planar arrangement where each chip would need its own pad in the same layer, to a three-dimensional stacking approach where a single pad can access multiple chips at different vertical levels through TSVs and RDLs, effectively using the vertical dimension to reduce the horizontal pad count
3Ease of operation
If redistribution layers with different patterns are formed on chip selection pads, then chip selection is enabled, but fabrication costs increase and fabrication management becomes complex
Solution Approach 1:
The patent segments the chip-selection functionality across multiple redistribution layers, with each RDL handling the connection to a specific chip. This segmentation allows each layer to have a simplified, standardized pattern that can be manufactured independently, reducing the overall fabrication complexity compared to creating one complex multi-layer pattern
Solution Approach 2:
The patent performs preliminary routing setup during the TSV formation stage, where via holes are strategically positioned to enable future RDL connections. This preliminary action prepares the structure in advance, making the subsequent RDL fabrication simpler and more manageable by pre-establishing the vertical connection pathways
Data Source
AI summary
A stack package may include a plurality of chips stacked with a plurality of layers; and a chip selection controller configured to provide a reference and chip selection control signal to the plurality of chips. Each chip may comprise: a reference signal controller configured to transmit the reference signal through a first line interconnecting the plurality of chips; a chip selection delay unit configured to control a delay timing point of the chip selection control signal to transmit the control result to each node of a second line interconnecting the plurality of chips; a delay-time-difference sensing unit configured to calculate a delay time difference between a signal applied to each node of the first and second line to generate chip selection information corresponding to the calculated delay time difference; and a memory unit configured to store the chip selection information.