Stack Semiconductor Package Signal Path Equalization
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Solution Overview
Problem
Stack packages face a decrease in data processing speed due to signal processing speed deviations among semiconductor chips and poor connections caused by sub-substrate warpage, limiting their ability to handle high-speed data processing.
Innovation Solution
A slim structured stack package design featuring a core layer with circuit wiring lines, semiconductor devices, resin layers, and via patterns that electrically connect the devices, ensuring consistent terminal part distances and preventing signal path delays, while using external mounting members for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to increase data storage capacity, then storage capacity is improved, but data processing speed decreases due to signal processing speed deviations
Solution Approach 1:
The patent divides the signal transmission path into multiple controlled segments by introducing a sub-substrate that separates the stack package into distinct layers. Each layer (first semiconductor chip, sub-substrate, second semiconductor chip) is independently controlled for signal path length, allowing segmentation of the overall signal transmission into manageable portions that can be individually optimized for equal length.
Solution Approach 2:
The patent changes the physical parameters of the package structure by controlling the thickness and dimensions of the sub-substrate and positioning semiconductor chips at specific heights. By adjusting these geometric parameters, the signal path lengths through via holes in different layers are equalized, compensating for the natural variations that would occur in a simple stacked configuration.
2Speed
If an additional sub-substrate is inserted to manufacture a stack package capable of processing data at a high speed, then data processing speed is improved, but poor connections may be formed in joints due to the warpage of the sub-substrate
Solution Approach 1:
The patent controls the warpage of the sub-substrate by precisely managing its thickness parameter and material properties. By setting the sub-substrate thickness to a specific range (0.5mm to 2.0mm in preferred embodiments), the structure maintains sufficient rigidity to prevent excessive warpage while still allowing for signal path length equalization, thus ensuring reliable connections.
Solution Approach 2:
The patent employs a composite structure consisting of the sub-substrate combined with resin layers and semiconductor chips. This composite construction distributes mechanical stresses and reduces overall warpage compared to using the sub-substrate alone, improving connection reliability while maintaining the signal path length control necessary for high-speed data processing.
3Length of stationary object
If a slim structure is designed for the stack package, then package size is reduced, but manufacturing precision requirements increase due to the need for precise signal path control
Solution Approach 1:
The patent achieves slim package dimensions by optimizing the thickness parameters of each layer (semiconductor chips, sub-substrate, resin layers). By controlling these parameters within specific ranges, the overall package thickness is minimized while maintaining sufficient precision for signal path length equalization. The sub-substrate thickness is specifically controlled to balance structural integrity with signal path control requirements.
Data Source
AI summary
A stack package includes a core layer having a first surface and a second surface, and including first circuit wiring lines; a first semiconductor device disposed on the second surface of the core layer; a first resin layer formed on the second surface of the core layer to cover the first semiconductor device; second circuit wiring lines formed on the first resin layer and electrically connected with the first semiconductor device; a second semiconductor device disposed over the first resin layer including the second circuit wiring lines and electrically connected with the second circuit wiring lines; a second resin layer formed on the second circuit wiring lines and the first resin layer to cover the second semiconductor device; and a plurality of via patterns formed to pass through the first resin layer and the core layer and electrically connecting the first circuit wiring lines and the second circuit wiring lines.