Stackable Capacitor Structure for 3D DRAM Integration
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Solution Overview
Problem
The integration of dynamic random access memory (DRAM) into logic devices is challenging due to the difficulty in combining transistors made in the front end of line (FEOL) process with capacitors made in the back end of line (BEOL) process, limiting the enhancement of reading performance and reliability, especially in achieving high storage capacitance and memory density.
Innovation Solution
A semiconductor structure is developed where both the transistor and capacitor are fabricated in the BEOL process, utilizing a stackable capacitor structure over the FEOL, which increases capacitance and allows for higher density and performance memory applications by breaking the planar area limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are made in FEOL process and capacitors are made in BEOL process, then the integration of DRAM into logic devices is achieved, but the reading performance and reliability cannot be enhanced due to process compatibility issues
Solution Approach 1:
The patent segments the capacitor structure into multiple components formed at different stages: the base capacitor structure is formed during FEOL, and additional capacitor layers are formed during BEOL. This segmentation allows each part to be optimized for its specific formation process while achieving overall integration.
Solution Approach 2:
The patent performs preliminary actions by forming the base capacitor structure and transistor during FEOL before the BEOL process begins. This preliminary formation of critical components enables subsequent BEOL processing to focus on enhancing rather than creating from scratch, improving both compatibility and performance.
2Quantity of substance
If planar capacitor structure is used, then the manufacturing process is simple, but the storage capacitance and memory density are limited
Solution Approach 1:
The patent transitions from a planar (2D) capacitor structure to a three-dimensional stacked structure by adding vertical layers during BEOL. This dimensional change increases the effective capacitance area without proportionally increasing planar footprint, thereby increasing storage capacitance while managing structural complexity through systematic layering.
Solution Approach 2:
The patent implements nesting by placing additional capacitor layers above the base capacitor structure formed in FEOL. The BEOL-formed layers are nested over the FEOL-formed layers, creating a stacked configuration that multiplies capacitance within a compact vertical space, effectively increasing storage capacity without linearly increasing device area.
3Productivity
If 3D stacked capacitor structure is implemented, then memory density and capacitance are increased, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges the FEOL and BEOL manufacturing processes by integrating capacitor formation steps across both process stages. Rather than treating them as separate, independent processes, the methodology combines them into a unified flow where FEOL forms the base structure and BEOL adds enhancement layers, thereby achieving 3D stacking without duplicating entire process sequences.
Solution Approach 2:
The patent applies universality by using the BEOL process for dual purposes: its primary function of forming interconnect metallization layers and its secondary function of forming additional capacitor structures. This multi-functionality allows the same BEOL tooling and process infrastructure to serve both interconnect and capacitor formation needs, reducing overall manufacturing complexity despite the increased 3D structure.
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a substrate, a front end of line (FEOL) structure, and a metallization structure. The FEOL structure is disposed over the substrate. The metallization structure is over the FEOL structure. The metallization structure includes a transistor structure, an isolation structure, and a capacitor. The transistor structure has a source region and a drain region connected by a channel structure. The isolation structure is over the transistor structure and exposing a portion of the source region, and a side of the isolation structure has at least a lateral recess vertically overlaps the channel structure. The capacitor is in contact with the source region and disposed conformal to the lateral recess. A method for manufacturing a semiconductor structure is also provided.