Stackable Microelectronic Packages with Vertical Interconnects
Solution Overview
Problem
Current microelectronic packaging technologies, such as chip-scale and die-stacked packages, face challenges in minimizing space occupation on circuit boards while maintaining efficient electrical connections and signal propagation, leading to increased complexity and cost in circuit panel design.
Innovation Solution
A microelectronic package design featuring a substrate with conductive elements projecting above one surface, electrically interconnected with both substrate contacts and microelectronic element contacts, and encapsulated with a major surface that exposes package contacts for interconnection, allowing for efficient stacking and reduced circuit panel requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If chip-scale packages are used to reduce the area occupied by packaged chips, then the area occupation is reduced, but the aggregate area occupied by several packaged chips becomes greater than or equal to the aggregate area of the individual chips
Solution Approach 1:
The patent transitions from a two-dimensional arrangement of chips on a circuit board to a three-dimensional stacked configuration. Multiple chips are mounted vertically on a single substrate, utilizing the vertical dimension to reduce the footprint area while maintaining functional connectivity through vertical interconnections.
Solution Approach 2:
The patent implements a hierarchical nesting structure where multiple chips are nested within a common package assembly. The chips are stacked one above another, with each chip nested in the vertical space above or below adjacent chips, creating a compact integrated unit that reduces overall area occupation.
2Area of stationary object
If die-stacked packages are used to conserve space on circuit panels, then space is conserved, but the circuit panel still requires conductors and elements for interconnections between individual packages
Solution Approach 1:
The patent merges multiple separate chip packages into a single integrated stacked package assembly. The chips are interconnected through vertical conductors within the package, eliminating the need for separate horizontal interconnections on the circuit board. This consolidation reduces both the area required and the complexity of external interconnections.
Solution Approach 2:
The patent extracts the interconnection function from the circuit board plane and relocates it to the vertical dimension within the package assembly. The conductors are taken out from the horizontal circuit board layer and repositioned as vertical interconnects between stacked chips, simplifying the circuit board layout.
3Ease of operation
If individual packages are mounted on a circuit panel, then each package can be handled separately, but the aggregate area occupied is greater and interconnections require more layers of metallic connections
Solution Approach 1:
The patent relocates interconnections from the horizontal plane (requiring multiple metal layers on the circuit board) to the vertical dimension (using through-substrate conductors and vertical interconnects). This dimensional shift reduces the number of metallic layers required on the circuit panel while maintaining ease of package handling as a unified assembly.
Data Source
AI summary
A microelectronic package having a substrate, a microelectronic element, e.g., a chip, and terminals can have conductive elements electrically connected with element contacts of the chip and contacts of the substrate. Conductive elements can be electrically insulated from one another for simultaneously carrying different electric potentials. An encapsulant can overlie the first surface of the substrate and at least a portion of a face of the microelectronic element remote from the substrate, and may have a major surface above the microelectronic element. A plurality of package contacts can overlie a face of the microelectronic element remote from the substrate. The package contacts, e.g., conductive masses, substantially rigid posts, can be electrically interconnected with terminals of the substrate, such as through the conductive elements. The package contacts can have top surfaces at least partially exposed at the major surface of the encapsulant.