Stackable MOM Capacitor Minimizing Parasitic Coupling
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Solution Overview
Problem
Existing capacitor arrays in integrated circuits face challenges in minimizing parasitic capacitance, which increases costs due to the need for large capacitance values and array areas, especially when designing with multiple capacitors.
Innovation Solution
A stackable metal-oxide-metal (MOM) capacitor array structure is implemented, where conductors are arranged in a specific configuration on a substrate with vias connecting them, minimizing parasitic capacitance by using a shared bottom plate as a shield and adjusting the connections and spacing of top and bottom plates to optimize capacitance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large capacitor geometries are used to reduce parasitic capacitance percentage, then parasitic capacitance control is improved, but array area and cost increase
Solution Approach 1:
The patent transitions from planar capacitor arrangement to three-dimensional stacked configuration. Multiple capacitor plates are arranged vertically along the first axis, with alternating polarity, creating capacitances in the vertical dimension while maintaining compact horizontal footprint. This dimensional change enables higher capacitance density without proportionally increasing array area.
Solution Approach 2:
The patent implements nested stacking where capacitor plates are arranged in alternating layers with shared interfaces. The first plurality of conductors and second plurality of conductors are stacked alternately, with each interface forming a capacitance. This nested arrangement maximizes capacitance per unit volume by utilizing the vertical space efficiently.
2Quantity of substance
If more capacitors are integrated in the array, then capacitance value is improved, but array area and cost increase
Solution Approach 1:
The patent achieves higher capacitance values by stacking capacitor plates vertically rather than expanding horizontally. Multiple interfaces between alternating conductor plates create multiple capacitances in series/parallel combinations, increasing total capacitance while maintaining compact horizontal dimensions.
Solution Approach 2:
The patent combines multiple capacitor units into a single integrated stacked structure. Adjacent capacitor units share common plates and vias, merging multiple capacitance elements into one compact array that achieves higher total capacitance without proportional area increase.
3Reliability
If top plate parasitic capacitance is minimized, then matching performance is improved, but device complexity increases
Solution Approach 1:
The patent extracts and separates the top plate from the main capacitor stack by positioning it above the uppermost plate. This isolation reduces unwanted parasitic coupling between the top plate and surrounding structures, improving matching performance while maintaining a systematic fabrication approach.
Solution Approach 2:
The patent introduces shield plates or ground structures as intermediaries between capacitor elements and surrounding circuitry. These intermediary structures act as barriers to reduce parasitic capacitance and electromagnetic coupling, improving matching performance without requiring fundamental changes to the capacitor design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance, allowing for higher density and efficiency in capacitor arrays without increasing costs, by using a shared bottom plate as a shield and optimizing the connections and spacing of top and bottom plates.
Implementation Method 1
using a shared bottom plate as a shield
Implementation Method 2
Capacitances are formed along the plurality of planes between the first plurality of conductors and the second plurality of conductors
Data Source
AI summary
A system including first and second plurality of conductors stacked along a first axis on a substrate. The first axis is perpendicular to a plane on which the substrate lies. In the first and second plurality of conductors, each conductor is connected to an adjacent conductor by one or more first vias arranged along the first axis. The first and second plurality of conductors are arranged in parallel along a second axis (i) perpendicular to the first axis and (ii) parallel to the plane on which the substrate lies. The first plurality of conductors respectively lie on a plurality of planes (i) perpendicular to the first axis and (ii) parallel to the plane on which the substrate lies. The second plurality of conductors respectively lie on the plurality of planes. Capacitances are formed along the plurality of planes between the first plurality of conductors and the second plurality of conductors.