Stackable Semiconductor Package with Supporting Element
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Solution Overview
Problem
Conventional stackable semiconductor packages are limited to a single chip and suffer from issues such as overhanging substrate portions that can cause vibration and cracking during wire bonding, restricting chip density and layout space due to the overhanging length limitations.
Innovation Solution
A stackable semiconductor package design incorporating two chips with separate substrates and molding compounds, along with an adhesive layer and additional wires, allowing for increased chip density and improved applicability, and optionally featuring a supporting element to stabilize the overhanging substrate during wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the area of the second substrate is increased to provide more layout space for second pads, then the layout space is improved, but the overhanging portion becomes longer and causes sway or vibration during wire bonding
Solution Approach 1:
The patent divides the substrate structure into multiple segments by introducing a supporting element that separates the overhanging portion from the main substrate body. This segmentation allows the overhanging portion to extend further while the supporting element provides localized stabilization, resolving the contradiction between increasing substrate area and maintaining stability during wire bonding.
2Length of stationary object
If the overhanging length is increased to provide more layout space, then the layout space is improved, but the substrate may crack under downward stress during wire bonding
Solution Approach 1:
The supporting element is positioned beforehand under the overhanging portion of the second substrate to provide mechanical support and distribute downward stress during wire bonding. This prior cushioning prevents the substrate from cracking while allowing the overhanging length to be extended for increased layout space.
3Device complexity
If only one chip is used in the package, then the manufacturing process is simpler, but the chip density and applicability are limited
Solution Approach 1:
The patent transitions from a single-chip horizontal layout to a multi-chip vertical stack configuration. By utilizing the vertical dimension, multiple chips can be integrated within the same package footprint, significantly increasing chip density and applicability while maintaining manageable manufacturing complexity through standardized bonding processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enables the integration of at least two chips, enhancing chip density and applicability while preventing substrate sway and cracking during wire bonding, even with extended overhanging lengths.
Implementation Method 1
The adhesive layer is used to attach the second surface of the second molding compound to the area not encapsulated by the first molding compound on the first surface of the first chip
Implementation Method 2
The first wires electrically connect the first surface of the first chip and the first surface of the first substrate
Implementation Method 3
The first molding compound encapsulates a part of the first surface of the first substrate, the first wires, and a part of the first surface of the first chip
Implementation Method 4
The second surface of the first chip is attached to the first surface of the first substrate by flip-chip bonding
Data Source
AI summary
A stackable semiconductor package includes a top package, a bottom package, an adhesive layer, a plurality of wires and a molding compound. A part of a surface of a chip of the bottom package is exposed. The top package is inverted, and is adhered to the chip of the bottom package with the adhesive layer. The wires electrically connect a substrate of the bottom package and a substrate of the top package. The molding compound encapsulates the top package, the bottom package, the adhesive layer,and the wires, and exposes a part of a surface of the substrate of the top package. Thus, the stackable semiconductor package includes at least two chips, thereby increasing the chip density and improving the applicability.