Stackable Wafer Level Package with Metal Pillars and Conductive Bumps
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving small-sized, lightweight, and high-performance electronic devices with reduced packaging costs, particularly in the development of wafer level chip size packages (WLCSPs), where efficient interconnectivity and cost-effective manufacturing methods are needed.
Innovation Solution
A wafer level package design incorporating a first semiconductor die with metal pillars, a second semiconductor die connected through conductive bumps and encapsulant, redistribution layers, and solder balls, with through-silicon vias and auxiliary metal pillars for enhanced electrical connectivity and reduced thickness and footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If conventional packaging technologies are used, then device performance can be maintained, but device size and weight cannot be sufficiently reduced
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked packaging by vertically stacking multiple semiconductor dies (first semiconductor die, second semiconductor die, third semiconductor die) with interconnect structures (metal pillars, conductive bumps, through-silicon vias) between them. This vertical integration reduces the horizontal footprint and overall device size while maintaining functionality.
Solution Approach 2:
The patent implements nested packaging by placing smaller semiconductor dies (second and third semiconductor dies) on top of larger dies (first semiconductor die), with encapsulant material nested around and between the dies. The redistribution layers are nested within the stack structure, creating a compact nested configuration that minimizes device volume.
2Ease of manufacture
If wafer level chip size package technology is implemented, then packaging cost is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary actions by pre-forming metal pillars on the first semiconductor die, pre-attaching the second semiconductor die with conductive bumps, and pre-forming through-silicon vias in the second and third semiconductor dies before final encapsulation. This staged approach allows for better alignment control and reduces manufacturing complexity compared to post-assembly modifications.
Solution Approach 2:
The patent segments the packaging process into distinct stages: forming metal pillars on the first die, attaching the second die with conductive bumps, forming through-silicon vias, attaching the third die, and final encapsulation. This segmentation allows each step to be optimized independently for precision and cost-effectiveness.
3Adaptability or versatility
If multiple semiconductor dies are stacked, then device functionality is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent uses universal interconnect structures (metal pillars, conductive bumps, through-silicon vias, redistribution layers) that serve multiple functions: electrical connection between dies, mechanical support, and signal routing. The encapsulant material provides multiple functions including protection, alignment, and stress relief. This multi-functionality reduces the need for additional specialized components and simplifies the overall manufacturing process.
Data Source
AI summary
A stackable wafer level package and a fabricating method thereof are disclosed. In the stackable wafer level package, bond pads (or redistribution layers) are arranged on a bottom semiconductor die, and metal pillars are formed on some of the bond pads positioned around the edges of the bottom semiconductor die. A top semiconductor die is electrically connected to the other bond pads, on which the metal pillars are not formed, positioned around the center of the bottom semiconductor die through conductive bumps. The metal pillars and the top semiconductor die are encapsulated by an encapsulant. A plurality of interconnection patterns electrically connected to the metal pillars are formed on the surface of the encapsulant. Solder balls are attached to the interconnection patterns. Due to this stack structure, the wafer level package is reduced in thickness and footprint. Therefore, the wafer level package is highly suitable for mobile applications.