Stacked 2D Material Tri-Gate Structure for Dense Vertical Transistors
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Solution Overview
Problem
Conventional semiconductor devices face challenges in accommodating reduced volume requirements while maintaining computational efficiency, as simply reducing device size is not sufficient to achieve high density configurations and improved performance.
Innovation Solution
The implementation of a stackable semiconductor device with a two-dimensional material layer, where a dielectric core is used to bond with 2D materials, enabling the formation of tri-gate devices with high-k dielectric and metal sidewalls, allowing for vertical nanometer-scale transistor channels and enhanced transistor speed through the use of materials like graphene.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor devices simply reduce device size, then volume requirements decrease, but computational throughput and density cannot be effectively improved
Solution Approach 1:
The patent transitions from planar 2D device architecture to vertical 3D architecture by stacking multiple semiconductor devices vertically. The tri-gate transistor structure extends the channel into the vertical dimension, allowing multiple active channels per footprint area, thereby increasing computational density and throughput without merely scaling down device dimensions
Solution Approach 2:
The patent implements nested structures where metal sidewalls are formed within dielectric material, and multiple tri-gate transistor channels are nested vertically around a central dielectric core. This nested arrangement maximizes the use of vertical space to achieve high device density while maintaining functional performance
2Volume of moving object
If device size is reduced to achieve compact form factors, then portability improves, but maintaining reliable computation becomes difficult
Solution Approach 1:
The patent employs composite material structures combining dielectric cores with 2D material channels (such as graphene or transition metal dichalcogenides), metal sidewalls for gating, and high-k dielectric layers. This composite approach enables compact vertical devices while maintaining electrical performance and computational reliability through the synergistic properties of different materials
Solution Approach 2:
The patent applies different materials and structures to specific regions: 2D materials provide high-mobility channels in critical transistor regions, metal sidewalls provide precise electrostatic control, and high-k dielectric provides effective gate insulation. This localized optimization ensures reliable computation in each functional region while maintaining overall device compactness
3Speed
If 2D material channels are used to enhance transistor speed, then computational throughput improves, but device fabrication complexity increases
Solution Approach 1:
The patent segments the device into distinct functional layers: dielectric core, metal sidewalls, 2D material channel, high-k dielectric, and gate electrode. This segmentation allows each component to be optimized independently and facilitates systematic fabrication processes, reducing overall complexity despite the advanced materials used
Solution Approach 2:
The dielectric core acts as an intermediary structure that enables the formation of tri-gate transistors with 2D material channels. It provides a template for depositing metal sidewalls and 2D materials in controlled sequences, simplifying the fabrication of complex vertical structures while maintaining high transistor speed through effective electrostatic control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of highly dense stacks of semiconductor devices with reliable computation, achieving improved transistor speed and accommodating arbitrary stack heights, thus addressing the need for compact and efficient semiconductor devices.
Implementation Method 1
a dielectric core that may receive and bond with 2D material during 2D material deposition
Implementation Method 2
forming a high-k dielectric layer on the two-dimensional material
Data Source
AI summary
Example implementations can include a device with a core including a first dielectric material, the core having a mesa structure, a first layer disposed over opposite faces of the mesa structure of the core, the first layer including a metal material, and a second layer disposed over the mesa structure of the core and the first layer, the second layer including a two-dimensional material. Example implementations can include a method of manufacturing a stackable semiconductor device with a two-dimensional material layer, by depositing, over a substrate, a base layer including a first dielectric material, forming, on the base layer, at least one core having a mesa structure, forming sidewalls on opposite vertical surfaces of the mesa structure of the core, depositing, over the core and the sidewalls, a semiconductor layer including a two-dimensional material, and encapsulating the core, the sidewalls, and the semiconductor layer.