Stacked 3D Memory Architecture for Low-Power Image Processing
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Solution Overview
Problem
Existing artificial reality devices face challenges in reducing power consumption and chip size while maintaining high-resolution image capture capabilities, particularly due to inefficiencies in data transmission and storage in 3D stacked memory architectures.
Innovation Solution
Implementing a customized 3D stacked memory with a low power DRAM die, a customized Network-on-Chip (NoC) architecture, and a memory controller, which eliminates the need for physical interface circuitry and impedance matching, and uses unidirectional/bidirectional links and out-of-order schedulers to optimize data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional memory architecture is used in artificial reality devices, then data transmission capability is sufficient, but power consumption is high
Solution Approach 1:
The patent transitions from traditional 2D memory architecture to 3D stacked memory architecture, stacking multiple memory dies vertically to increase storage capacity and improve data transmission efficiency while reducing power consumption through shorter signal paths and reduced capacitance
Solution Approach 2:
The memory system is divided into multiple independent memory banks across different dies, allowing parallel access to multiple banks simultaneously, which improves data transmission capability while the segmented architecture reduces the load on individual banks, lowering power consumption
2Area of stationary object
If chip density is increased to reduce chip size, then package size is reduced, but power consumption increases
Solution Approach 1:
The patent uses 3D stacking to achieve high density without increasing planar chip area, organizing memory banks across multiple vertically stacked dies to maximize space utilization while maintaining low power consumption through efficient inter-die connectivity
Solution Approach 2:
The patent implements selective activation of memory banks based on workload requirements, enabling the system to use only the necessary portion of available memory capacity at any given time, which reduces power consumption while maintaining the capability for high-density storage when needed
3Measurement precision
If high-resolution image capture is enabled, then image quality is improved, but power consumption increases
Solution Approach 1:
The patent implements continuous data transfer pipelines between the image sensor and 3D stacked memory, eliminating idle periods and ensuring that data is processed and stored efficiently without unnecessary power-consuming operations, maintaining high-resolution capture capability with optimized power usage
Solution Approach 2:
The patent divides the high-resolution image data into smaller chunks that can be processed and stored in parallel across multiple memory banks, distributing the processing load and reducing the peak power consumption required for high-resolution image capture
Data Source
AI summary
A headset includes a camera a 3D stacked memory configured to store image data captured by the camera, and a System-on-Chip (SoC) configured to process the image data stored in the 3D stacked memory. The 3D stacked memory includes a plurality of first drivers/receivers and a plurality of memory banks that are accessible in parallel. Each memory bank is accessible via a corresponding first driver/receiver. The SoC includes a memory controller with a plurality of second drivers/receivers. The plurality of the second drivers/receivers of the SoC are respectively connected to the plurality of the first drivers/receivers of the 3D stacked memory by a plurality of channels. The SoC and the 3D stacked memory are vertically stacked together. The plurality of the memory banks include at least eight memory banks.