Stacked Imaging Sensor Circuit Partitioning for Smaller AD Chips
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In stacked-type imaging apparatuses, the size reduction of AD conversion circuits is challenging due to their complexity and the need for smaller chip sizes, which hinders the miniaturization of both the circuits and the imaging apparatus.
Innovation Solution
The solution involves a layered structure where pixel circuits for optical-to-electrical conversion are on one substrate, and AD converters for signal processing are on a lower substrate, with encoding, holding, and output units distributed across multiple substrates to optimize size reduction and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the AD conversion circuit is integrated on the same chip as the pixel array, then signal processing efficiency is improved, but the chip size increases due to the large number of transistors required
Solution Approach 1:
The imaging apparatus divides the chip into multiple chips, with the pixel array formed on a first chip and the AD conversion circuit formed on a second chip. This segmentation allows each chip to be optimized independently, reducing the size of individual chips while maintaining the functional integration benefits for signal processing efficiency.
2Measurement precision
If the number of pixels is increased to improve image quality, then resolution is improved, but the chip size increases due to more pixel circuits and associated processing circuits
Solution Approach 1:
By segmenting the imaging apparatus into multiple chips with the pixel array on one chip and processing circuits on separate chips, the patent enables higher pixel counts for improved image quality without proportionally increasing the size of individual chips. The processing functions are distributed to dedicated chips, allowing the pixel chip to remain compact.
3Area of stationary object
If the AD conversion circuit is miniaturized to reduce chip size, then chip size is reduced, but circuit complexity increases making miniaturization difficult
Solution Approach 1:
The patent separates the complex AD conversion circuit from the pixel array chip and places it on a dedicated second chip. This segmentation isolates the circuit complexity to a separate component, allowing the pixel chip to be miniaturized without being constrained by the transistor density requirements of the AD conversion circuit.
Solution Approach 2:
The patent transitions from a two-dimensional integration approach to a three-dimensional stacked configuration, with the pixel array chip and processing chip arranged in different layers. This vertical stacking allows both chips to be miniaturized in the planar dimension while accommodating complex circuits through the additional vertical dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a significant reduction in the size of both the chip and the imaging apparatus, improving their miniaturization and efficiency while maintaining effective signal processing.
Implementation Method 1
pixel circuits that each output an electric charge signal generated by receiving incident light and performing optical-to-electrical conversion on the incident light
Data Source
AI summary
An imaging apparatus and an electronic device with reduced size are disclosed. In one example, an imaging apparatus includes pixel circuits, an AD converter, an encoding unit, a holding unit, and an output unit. The pixel circuits output an electric charge signal generated from incident light. The AD converter compares the electric charge signal with a reference signal for each of the pixel circuits, and outputs, as a conversion result, a code input signal at a time when a comparison result has been inverted. The encoding unit encodes the conversion result from the AD converter. The holding unit holds an encoding result. The output unit outputs the encoding result held by the holding unit. The pixel circuits are disposed in a first substrate. The AD converter is disposed in a second substrate that is stacked in a lower layer of the first substrate.