Stacked Anti-Fuse OTP Memory Cell for Smaller, Simpler Arrays
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Solution Overview
Problem
One-time programmable (OTP) memory devices face issues of large storage area, low integration, complex manufacturing process, and high manufacturing cost due to their reliance on the dynamic random access memory (DRAM) structure with selective transistors and capacitors, which have irreversible dielectric breakdown.
Innovation Solution
A semiconductor structure is designed with a selective transistor and an anti-fuse bit structure where the anti-fuse bit is positioned above the transistor, reducing horizontal space occupation and integrating the capacitor structure into a second layer, allowing for simultaneous formation of electrodes and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the OTP memory adopts the DRAM structure with selective transistor and capacitor, then the irreversible dielectric breakdown can be achieved for data storage, but the storage area becomes large and integration becomes low
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional stacked structure where the capacitor is positioned vertically above the transistor. This vertical stacking in the Z-dimension reduces the horizontal footprint of each memory cell, thereby decreasing the storage area while maintaining the necessary functional components for reliable data storage through dielectric breakdown.
Solution Approach 2:
The capacitor structure is nested above the transistor structure, with the capacitor's bottom electrode integrated with or connected to the transistor's drain region. This nested arrangement allows the capacitor to occupy the vertical space above the transistor rather than requiring separate horizontal space, reducing overall cell area while preserving both the transistor's switching function and the capacitor's storage function.
2Reliability
If the OTP memory uses separate formation processes for transistor and capacitor, then the device functionality can be achieved, but the manufacturing process becomes complex and cost increases
Solution Approach 1:
The patent merges the formation processes of the transistor and capacitor by integrating the capacitor's bottom electrode formation with the transistor's drain region formation. Both structures are formed simultaneously using the same semiconductor processing steps, including doping, oxidation, and deposition processes, thereby simplifying the manufacturing process and reducing the number of separate fabrication stages required.
Solution Approach 2:
The drain region of the transistor serves dual functions: as the active drain region for transistor operation and as the bottom electrode of the capacitor. This multi-functional design eliminates the need for separate electrode formation processes, reducing manufacturing complexity while maintaining both the transistor's switching capability and the capacitor's data storage capability through dielectric breakdown.
3Ease of manufacture
If the capacitor structure is formed in the same plane as the transistor, then the manufacturing process can be simplified, but the memory cell size increases
Solution Approach 1:
The patent resolves this contradiction by moving the capacitor structure from the same plane as the transistor to a vertical stacking arrangement in the third dimension. The capacitor is positioned above the transistor with its bottom electrode connected to the drain region, allowing simplified manufacturing through integrated formation processes while minimizing the horizontal footprint of the memory cell.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces memory cell size, improves integration, simplifies the manufacturing process, and enhances reliability by stabilizing programming voltage, thus addressing the limitations of existing OTP memory technologies.
Implementation Method 1
a breakdown state and a non-breakdown state of the anti-fuse bit structure are used to represent different stored data
Data Source
Figure 1~3
Figure 4~6
Figure 7~8B
AI summary
Provided are a semiconductor structure and a method for manufacturing the same, a memory and a method for operating the same. The semiconductor structure includes a substrate having a plurality of active areas close to a surface of the substrate; a gate structure located in a first structure layer on the substrate, in which the gate structure and the active areas constitute a selective transistor; and an anti-fuse bit structure located in a second structure layer on the first structure layer, and connected with an active area of one selective transistor through a first connecting structure, in which a breakdown state and a non-breakdown state of the anti-fuse bit structure represent different stored data.