Stacked Semiconductor Bonding Pad Structure Against Delamination

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Solution Overview

Problem

Existing semiconductor packages face challenges in achieving high integration, miniaturization, and high performance while maintaining efficient electrical connectivity between stacked semiconductor chips.

Innovation Solution

A semiconductor chip design featuring a through electrode with a bonding pad structure that includes a first conductive pad protruding outwardly relative to a second conductive pad, surrounded by a pad insulating layer, and a semiconductor package with stacked chips connected via bonding pads and insulating layers, allowing for efficient electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional bonding pad structure is used, then the manufacturing process is simple, but delamination occurs at the bonding interface reducing reliability

Engineering Contradiction:
Improvebonding reliabilityVSAvoidbonding pad structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bonding pad is divided into multiple conductive pads stacked vertically, with each pad serving a specific function. The first conductive pad provides electrical connection to the through electrode, while the second conductive pad forms part of the bonding interface. This segmentation allows the structure to prevent delamination while maintaining manufacturing feasibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bonding pad structure transitions from a conventional planar design to a three-dimensional stacked configuration. The outer portion of the first conductive pad extends laterally beyond the second conductive pad, creating an overlapping structure in the horizontal dimension that mechanically reinforces the bonding interface and prevents delamination.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the outer portion of the first conductive pad is extended laterally, then delamination is suppressed through thermal expansion, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvebonding interface stabilityVSAvoidpad alignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The structure utilizes thermal expansion parameters of the conductive pad material to generate external force during bonding. The extended outer portion of the first conductive pad is designed to expand laterally under thermal conditions, creating compressive force on the bonding interface that suppresses delamination and improves bonding reliability.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances electrical connectivity and facilitates high integration and miniaturization of semiconductor packages, improving performance and reliability.

Implementation Method 1

the outer portion of the first conductive pad thermally expands to provide an external force that suppresses delamination between insulating layers

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS12604686B2Semiconductor chip and semiconductor package including the same
Publication Date: 2026.04.14 SAMSUNG ELECTRONICS CO LTD
  • US12604686B2 patent drawing
  • US12604686B2 patent drawing
  • US12604686B2 patent drawing

AI summary

A semiconductor chip and a semiconductor package, the semiconductor chip includes a semiconductor substrate; a through electrode penetrating the semiconductor substrate; a bonding pad including a first conductive pad connected to the through electrode, and a second conductive pad on a central portion of the first conductive pad, an outer portion of the first conductive pad protruding outwardly relative to a sidewall of the second conductive pad; and a pad insulating layer on the semiconductor substrate and surrounding a sidewall of the first conductive pad and the sidewall of the second conductive pad.