Stacked Capacitive C-Element Circuits for Low-Voltage Asynchronous Logic
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Solution Overview
Problem
Traditional asynchronous logic circuits face challenges in operating efficiently at low voltage conditions and require significant area and power due to the stack of devices between the supply and ground rails, limiting their performance and throughput.
Innovation Solution
The development of asynchronous circuits using threshold gates and majority/minority gates with capacitive input circuits, which reduce the stack of devices and enable operation at lower power supply levels, achieving area reduction and higher throughput by utilizing linear or nonlinear capacitors and adjustable threshold settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional asynchronous logic circuits use stacks of transistors between power supply rail and ground rail, then the circuits can be implemented with standard logic components, but the area occupied by the device increases and power consumption increases
Solution Approach 1:
The patent transitions from planar capacitor layouts to three-dimensional stacked capacitor structures. Multiple capacitor plates are arranged vertically between the power supply rail and ground rail, utilizing the third dimension (vertical stacking) to increase capacitance density without increasing the horizontal area occupied by the device.
Solution Approach 2:
The patent employs paraelectric materials as the dielectric layer in the capacitor structure. These materials provide non-linear capacitance characteristics that enable the circuit to achieve the desired logic functionality with reduced area and power consumption compared to traditional linear capacitor implementations.
2Ease of manufacture
If traditional asynchronous logic circuits use stacks of transistors between power supply rail and ground rail, then the circuits can be implemented with standard logic components, but the power consumption increases
Solution Approach 1:
The patent changes the electrical parameters of the circuit by introducing non-linear paraelectric capacitors with voltage-dependent capacitance. This non-linear behavior allows the circuit to operate efficiently at lower power supply voltages and reduces static power consumption by optimizing the charge-discharge characteristics of the capacitive elements.
Solution Approach 2:
The stacked three-dimensional capacitor structure increases the effective capacitance within a smaller area, allowing the circuit to maintain its functionality with fewer transistors and reduced power consumption compared to traditional planar implementations.
3Use of energy by stationary object
If asynchronous logic circuits operate at low voltage conditions, then power consumption is reduced, but the traditional stack of devices between supply and ground rails limits performance and throughput
Solution Approach 1:
The patent uses vertically stacked capacitor plates to increase capacitance density, enabling low-voltage operation while maintaining sufficient charge storage capacity to support high-speed switching and high throughput performance.
Solution Approach 2:
The use of paraelectric materials with non-linear dielectric properties enables the circuit to achieve low-voltage operation with improved switching characteristics, thereby maintaining high throughput while reducing power consumption.
4Area of stationary object
If the stack of devices between supply and ground rails is reduced, then area is reduced and operation at lower power supply levels is enabled, but traditional asynchronous logic requires significant stack height
Solution Approach 1:
The patent utilizes three-dimensional stacked capacitor structures that efficiently use vertical space, reducing the horizontal area occupied by the device while managing the vertical stack height through optimized capacitor plate arrangements and integration with the logic circuit layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These circuits achieve a 3x area reduction and 2x higher throughput compared to traditional asynchronous circuits, allowing operation at less than 1V, with the ability to function as synchronous circuits when input signals are used as clock signals.
Implementation Method 1
the first capacitor includes a first terminal coupled to the first input and a second terminal coupled to the summing node, the second capacitor includes a third terminal coupled to the second input and a fourth terminal coupled to the summing node
Data Source
AI summary
Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.