Stacked Unit Capacitor Structure for High Capacitance Density
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Solution Overview
Problem
The challenge is to create a capacitor with high capacity while maintaining a small size, as demanded by the trend of miniaturization in electronic products.
Innovation Solution
The capacitor design involves a substrate with unit capacitor cells that include lower and upper electrodes, connected through internal connection layers and external electrodes, forming a high-density electrode structure in a compact space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the capacitor size is reduced to meet miniaturization demands, then the device footprint is reduced, but the capacitance capacity decreases
Solution Approach 1:
The patent transitions from planar electrode arrangement to three-dimensional vertical stacking of multiple electrode layers. Multiple unit capacitor cells are stacked in the vertical direction, allowing capacitance to scale with height rather than just surface area. This dimensional change enables high capacitance in a compact footprint by utilizing the third dimension (thickness direction) for electrode arrangement.
Solution Approach 2:
The capacitor is divided into multiple unit capacitor cells, each containing discrete lower and upper electrodes separated by dielectric layers. These segmented units are stacked and connected through internal connection layers, allowing independent optimization of each cell while achieving high total capacitance through cumulative effect of multiple segments in series/parallel configuration.
2Quantity of substance
If electrodes are arranged at high density to increase capacitance, then capacitance capacity increases, but equivalent series inductance increases
Solution Approach 1:
By arranging electrodes vertically in stacked layers rather than spreading them horizontally, the patent reduces the loop area for current flow. The vertical stacking minimizes the horizontal distance between return paths, thereby reducing parasitic inductance while maintaining high capacitance density through vertical electrode proximity.
Solution Approach 2:
Adjacent electrodes from different unit capacitor cells are connected through internal connection layers to form continuous conductive paths. This merging of electrode structures creates optimized current flow paths that reduce equivalent series inductance while the combined capacitance of multiple cells increases total capacity.
3Quantity of substance
If multiple unit capacitor cells are stacked to increase capacitance, then capacitance capacity increases, but manufacturing complexity increases
Solution Approach 1:
The capacitor structure is segmented into standardized unit capacitor cells with consistent electrode-dielectric-electrode layers. This modular segmentation allows repeated formation of identical units through systematic processing steps, making the manufacturing of multi-cell stacked structures more manageable and scalable despite the increased number of components.
Solution Approach 2:
Internal connection layers are formed in advance during the manufacturing process to pre-establish connection paths between stacked unit capacitor cells. By preparing these connection structures beforehand, the patent simplifies the final assembly and reduces the complexity of creating inter-cell electrical connections after stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for high capacitance to be achieved in a small area, reducing equivalent series resistance and inductance, and enhancing breakdown voltage while minimizing the risk of breakdown phenomena.
Implementation Method 1
the lower electrode included in a first unit capacitor cell among the unit capacitor cells is connected to the upper electrode included in a second unit capacitor cell among the unit capacitor cells
Data Source
AI summary
An aspect of the present disclosure provides a capacitor including: a substrate; and a plurality of unit capacitor cells disposed on the substrate, wherein each of the unit capacitor cells includes: a lower electrode; and an upper electrode disposed on the lower electrode, the lower electrode included in a first unit capacitor cell among the unit capacitor cells is connected to the upper electrode included in a second unit capacitor cell among the unit capacitor cells.