Stacked Capacitors in Die Stacks for Power Delivery

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Semiconductive device miniaturization poses challenges for locating passive devices, such as capacitors, in proximity to other structures within stacked-die architectures, leading to inefficiencies in power delivery due to increased decoupling loop-inductance paths.

Innovation Solution

The integration of decoupling capacitors at the stacked-die level, electrically coupled to semiconductive devices, reduces decoupling loop-inductance by creating a vertical power rail that connects capacitors across multiple levels, ensuring capacitors are close to the semiconductive devices they service, thereby enhancing power-delivery efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductive devices are miniaturized and stacked vertically, then device density and integration are improved, but the distance between passive devices (capacitors) and active devices increases, worsening power delivery efficiency

Engineering Contradiction:
Improvedevice densityVSAvoidpower delivery efficiency
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent transitions from planar placement of capacitors to vertical stacking, moving the solution into the third dimension. Capacitors are positioned at multiple stacked levels (first level, second level, third level) corresponding to different die levels, creating a vertical power delivery network that reduces inductance while maintaining high device density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where capacitors are integrated within the stacked-die architecture itself. Each die level has associated capacitors positioned in close proximity, creating a hierarchical nesting pattern that embeds passive devices within the active device stack, minimizing separation distance while maximizing integration.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Loss of energy

If capacitors are placed close to semiconductive devices in stacked architecture, then power delivery efficiency is improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvepower delivery efficiencyVSAvoidstacked-die architecture complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent divides the power delivery system into segmented layers, with capacitors and dies organized at discrete levels (first level, second level, third level). Each level is independently structured with its own capacitors positioned near corresponding dies, allowing modular manufacturing and assembly while achieving close proximity for efficient power delivery.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent resolves complexity by utilizing the vertical dimension to organize components systematically. Instead of complex lateral routing, capacitors are positioned directly above or below dies in the vertical stack, simplifying interconnections through vertical vias and reducing the overall complexity of power delivery network routing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11121074B2Packaged die stacks with stacked capacitors and methods of assembling same
Publication Date: 2021.09.14 SK HYNIX NAND PRODUCT SOLUTIONS CORP
  • US11121074B2 patent drawing
  • US11121074B2 patent drawing
  • US11121074B2 patent drawing

AI summary

A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.