Stacked Standard Cell Layout for Isolation Without Height Growth
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Solution Overview
Problem
Stacked integrated circuit devices face increased device size due to the need for extra space for electrical isolation between adjacent standard cells, which is not efficiently addressed by existing technologies.
Innovation Solution
The design of stacked standard cells where only one of two adjacent cells has its output via adjacent to the cell boundary, eliminating the need for additional space between output vias and optimizing power line widths to reduce overall device height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked standard cells are arranged with output vias adjacent to cell boundaries for high integration density, then integration density is improved, but extra space must be provided for electrical isolation between adjacent cells, increasing device size
Solution Approach 1:
The patent applies asymmetry by configuring adjacent standard cells differently with respect to output via placement. Specifically, in a pair of adjacent standard cells, only one cell has its output via positioned adjacent to the shared cell boundary, while the other cell's output via is positioned away from the boundary. This asymmetric configuration eliminates the need for additional isolation space between cells while maintaining electrical isolation, thereby resolving the contradiction between high integration density and increased device size.
2Reliability
If additional space is provided between output vias of adjacent standard cells for electrical isolation, then electrical isolation is improved, but cell height increases
Solution Approach 1:
The asymmetric via placement configuration ensures that output vias of adjacent standard cells do not overlap or come into conflict, providing sufficient electrical isolation without requiring additional vertical space. By positioning the output via of only one adjacent cell near the boundary, the design achieves reliable electrical isolation while avoiding the need to increase cell height.
3Length of stationary object
If power line widths are optimized to reduce overall device height, then device height is reduced, but power delivery capability may be affected
Solution Approach 1:
The patent optimizes power line width as a design parameter to achieve the desired balance between device height and power delivery capability. By carefully selecting the power line width within specific ranges, the design reduces device height while maintaining sufficient power delivery capability to support the stacked standard cell configuration.
Data Source
AI summary
Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.