Stacked Cell Transistor Gate Dielectric for Resistance Control
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Solution Overview
Problem
Current nonvolatile memory devices and neuromorphic devices face challenges in precisely setting channel resistance levels and achieving high data retention stability with a high degree of integration.
Innovation Solution
The implementation of a nonvolatile memory device and neuromorphic device design featuring FinFET structure transistors with a gate dielectric layer comprising tunneling, charge trap, and blocking layers, along with a channel layer and buffer layers, allows for precise control of channel resistance through voltage manipulation, enhancing integration and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level channel resistance is implemented for multi-bit data storage, then storage capacity is improved, but precision in setting channel resistance levels deteriorates
Solution Approach 1:
The gate dielectric layer is segmented into multiple distinct layers (tunneling gate dielectric layer, charge trap gate dielectric layer, blocking gate dielectric layer), each contributing differently to channel resistance control. This segmentation enables precise manipulation of resistance levels through selective electron trapping in different layers, achieving both multi-bit storage capacity and precise resistance control
Solution Approach 2:
The patent changes physical parameters of the gate dielectric layer (thickness, material composition, layer structure) to precisely control electron tunneling and trapping behavior. By adjusting these parameters, multiple stable resistance states are achieved, enabling precise channel resistance setting for multi-bit storage
2Productivity
If stacked cell transistors are used to improve degree of integration, then device density is improved, but data retention stability deteriorates
Solution Approach 1:
Multiple cell transistors are nested vertically by stacking them along the vertical direction, sharing common bit lines and source lines. This nesting approach increases device density while maintaining data retention stability through the robust gate dielectric structure that ensures reliable electron trapping in each stacked transistor
Solution Approach 2:
The gate dielectric layer uses composite material structure with different dielectric materials (tunneling dielectric, charge trap dielectric, blocking dielectric) stacked together. This composite structure provides both the electrical characteristics needed for stable data retention and the physical structure supporting stacked transistor configuration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables precise control of channel resistance levels, improving data retention stability and integration, and can be applied to neuromorphic devices as synapses, enhancing their functionality.
Implementation Method 1
a tunneling gate dielectric layer through which electrons tunnel
Implementation Method 2
a charge trap gate dielectric layer which traps tunneled electrons
Data Source
AI summary
A nonvolatile memory device includes a gate line extending in a first horizontal direction; a gate electrode of a pillar shape extending in a vertical direction from the gate line; a plurality of bit lines and a plurality of source lines extending in parallel in a second horizontal direction perpendicular to the first horizontal direction, the plurality of bit lines and the plurality of source lines being stacked in the vertical direction; and a plurality of cell transistors vertically stacked to surround an outer side surface of the gate electrode between the plurality of bit lines and the plurality of source lines. Each of the cell transistors includes a gate dielectric layer which surrounds the outer side surface of the gate electrode and a channel layer which surrounds an outer side surface of the gate dielectric layer.