Stacked CFET CMOS Layout to Reduce Threshold-Voltage Variation
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Solution Overview
Problem
Existing semiconductor devices face layout-dependent effects (LDEs) such as increased rounding of structures and threshold-voltage variation due to substantial step-changes in the intersection-location of cell regions with differing heights in uniform CMOS architectures.
Innovation Solution
A mixed CMOS architecture is employed, featuring stacked half-height CFET cell regions with homogeneous dopant types along one axis and heterogeneous dopant types along another, minimizing substantial step-changes in intersection-locations, thereby reducing LDEs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform CMOS architecture with cell regions of differing heights is used, then device functionality is achieved, but layout-dependent effects such as increased rounding of structures and threshold-voltage variation occur due to substantial step-changes in intersection-locations
Solution Approach 1:
The patent transitions from a two-dimensional planar cell layout to a three-dimensional stacked cell architecture. By stacking cell regions vertically (adding the Z-dimension), the design eliminates substantial step-changes in intersection-locations that cause LDEs, while maintaining the necessary functionality of different cell types.
Solution Approach 2:
The patent applies different dopant types (n-type and p-type) to specific regions within the stacked structure. The first and second active regions have different dopant types, creating local quality variations that enable complementary transistor functionality while maintaining uniform intersection-locations throughout the structure.
2Adaptability or versatility
If stacked channel structures are formed with different dopant types, then complementary transistor functionality is achieved, but process complexity increases
Solution Approach 1:
The patent divides the stacked structure into distinct segments: first active regions with first dopant types and second active regions with second dopant types. This segmentation allows independent optimization of each transistor type while maintaining a unified stacked architecture, reducing overall process complexity.
Solution Approach 2:
The patent uses composite doping strategies where different dopant types are integrated into the stacked channel structure. By combining n-type and p-type doped regions in a vertical stack, the design achieves complementary transistor functionality (NFET and PFET) within a single integrated structure.
Data Source
AI summary
A method (of forming a semiconductor device) includes: forming first, second and third channel-stacks each including interleaved precursor-active layers and first sacrificial layers being plus an isolation boundary layer above which is some but not all of the first sacrificial layers; and each of the channel-stacks being separated from nearest other structures by corresponding first and second recesses; forming first source/drain (S/D) features configured with a first dopant type including: partially filling the first and second recesses of the second channel-stack with a first S/D material; and filling the first and second recesses of the third channel-stack with the first S/D material; and forming second S/D features configured a second dopant type including: further filling the first and second partially-filled recesses of the second channel-stack with a second S/D material; and filling the first and second recesses of the first channel-stack with the second S/D material.