Stepped Stacked CFET Gate Coupling for SRAM Latch Cross-Couples
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving complex signal connections between source/drain regions of complementary field-effect transistors (CFETs), particularly in stacked configurations, which complicates the implementation of latch cross-couple connections in SRAM cells due to the complexity of connecting gate layers of p-type and n-type FETs.
Innovation Solution
The solution involves constructing a semiconductor structure with a stacked and stepped field effect transistor (FET) configuration, where one FET is stacked over the other, with a stepped or tapered device layer, allowing for an electrical connection between the gates of the FETs at the stepped portion, and optionally incorporating a floating gate, to simplify the latch cross-couple connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If stacked CFET configuration is used to increase device density, then area consumption is reduced, but signal connection complexity between source/drain regions increases
Solution Approach 1:
The patent transitions from planar side-by-side transistor arrangement to vertical stacking configuration, utilizing the third dimension (vertical axis) to increase device density. The CFET structure stacks n-type and p-type FETs vertically with shared gate, reducing footprint area while the stepped device layers and isolation structures manage the complexity of interconnections in this new dimensional arrangement.
2Device complexity
If conventional planar FET arrangement is used, then signal connections are simpler, but integration density and device packing efficiency decrease
Solution Approach 1:
The invention moves from two-dimensional planar arrangement to three-dimensional vertical stacking, achieving higher integration density by utilizing vertical space. The CFET structure with stacked n-type and p-type FETs connected through isolation layers and contact structures enables this dimensional transition, sacrificing connection simplicity for substantial gains in device packing efficiency.
3Productivity
If stacked CFET with common gate is used, then device density increases, but providing signal connections to lower-level source/drain regions becomes complex
Solution Approach 1:
The patent divides the device into distinct segmented layers: upper-level FET, lower-level FET, isolation layers, and contact structures. This segmentation allows independent fabrication and connection establishment at different vertical levels, making the manufacturing process more manageable despite the increased device density achieved through stacking.
Solution Approach 2:
Isolation layers and contact structures serve as intermediary elements that facilitate signal connections between the lower-level source/drain regions and upper-level circuits. These intermediaries simplify the fabrication process by providing defined pathways and interfaces for electrical connections in the vertically stacked configuration.
4Reliability
If FinFET structure is used instead of planar FET, then control over channel and reduction of leakage current is improved, but device structure complexity increases
Solution Approach 1:
The FinFET structure introduces a three-dimensional fin geometry with gate wrapping around the fin, creating a curved/gate-all-around configuration that enhances electrostatic control over the channel. This curved structure reduces leakage current by improving field effect control, at the cost of increased structural complexity compared to planar FETs.
Data Source
AI summary
A semiconductor structure is presented having a first field effect transistor (FET) including a first device layer, a second FET including a second device layer, where the first device layer has a stepped portion with respect to the second device layer, and an electrical connection between a gate of the first FET and a gate of the second FET at the stepped portion of the first device layer. The first FET is stacked over the second FET. The second device layer is larger than the first device layer. The gate of the first FET is positioned above the first device layer having a stepped portion.