Stacked CFET Gate Liner Layout for Independent Gates
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Solution Overview
Problem
Conventional complementary field effect transistors (CFETs) face challenges in achieving independent gates and reducing metal volume to lower parasitic capacitance, particularly in stacked nanosheet configurations.
Innovation Solution
A semiconductor structure is designed with a second nanosheet device stacked over a first nanosheet device, where each nanosheet has a side contacting a dielectric material and a functional gate-containing liner, and sacrificial liners are replaced with functional gate structures, forming independent gates and reducing metal volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional CFET stacking is used to achieve smaller scale devices, then device miniaturization is improved, but independent gate control becomes difficult to achieve
Solution Approach 1:
The patent divides the CFET structure into separate n-type and p-type nanosheet stacks, each with its own independent gate structure. This segmentation allows each transistor type to have dedicated gate control while maintaining compact vertical stacking, resolving the contradiction between miniaturization and independent gate control.
Solution Approach 2:
The patent transitions from planar gate control to vertical stacking with gate-all-around structures. By utilizing the vertical dimension for stacking multiple nanosheets and implementing gates that wrap around channels in three dimensions, the patent achieves both small device footprint and independent gate control through spatial reconfiguration.
2Reliability
If conventional CFET gate structure is used, then device functionality is achieved, but large gate metal volume causes high parasitic capacitance
Solution Approach 1:
The patent changes the physical parameters of the gate structure by implementing thinner gate metal layers and optimizing gate material composition. These parameter changes reduce gate metal volume while maintaining sufficient gate control over the channel, thereby reducing parasitic capacitance without sacrificing device functionality.
Solution Approach 2:
The patent employs composite gate structures combining multiple materials with different properties (e.g., high-k dielectric materials with metal gates). This composite approach enables effective gate control with reduced metal volume, lowering parasitic capacitance while preserving essential device functionality.
Data Source
AI summary
A semiconductor structure is provided that includes a second nanosheet device of a second conductivity type stacked over a first nanosheet device of a first conductivity type that is different from the second conductivity type. Each of the first and second nanosheet devices includes at least one semiconductor channel material nanosheet. One side of the least one semiconductor channel material nanosheet of both the first and second nanosheet devices contacts a dielectric material, while another side of the least one semiconductor channel material nanosheet of both the first and second nanosheet devices contacts a functional gate-containing liner that extends laterally to connect to a gate contact of each first and second nanosheet device.