Stacked CFET Ribbon Channels With Alternate Materials on One Wafer
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Solution Overview
Problem
Current methods for fabricating stacked transistor structures with alternate doping profiles, such as NMOS and PMOS layers, face challenges including increased defects and costs due to the need for secondary substrates and limited integration capabilities, particularly when using layer transfer techniques.
Innovation Solution
The integration of different channel materials and gate materials in stacked transistor structures is achieved through the regrowth of channels from epitaxial structures, using sacrificial ribbons made of silicon or silicon germanium, allowing for the creation of discontinuous crystalline structures with varying doping levels, and enabling the use of different materials on the same wafer without the need for secondary substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If layer transfer techniques are used to fabricate stacked transistor structures with alternate doping profiles, then the ability to create NMOS and PMOS layers is achieved, but defects and costs increase due to the need for secondary substrates
Solution Approach 1:
The patent extracts and removes the sacrificial ribbons (first channel material) from the structure, leaving voids that are subsequently filled with different channel materials. This extraction approach eliminates the need for secondary substrates while enabling alternate doping profiles, thereby reducing defects associated with layer transfer techniques.
Solution Approach 2:
The sacrificial ribbons serve as intermediary structures that enable the formation of stacked transistor structures with alternate doping profiles. These ribbons are temporarily introduced, used as templates for epitaxial growth, and then removed, allowing different channel materials to be integrated without requiring secondary substrates.
2Adaptability or versatility
If layer transfer techniques are used to fabricate stacked transistor structures with alternate doping profiles, then the ability to create NMOS and PMOS layers is achieved, but costs increase due to the need for secondary substrates
Solution Approach 1:
By extracting and removing the sacrificial ribbons, the patent eliminates the need for expensive secondary substrates. This approach allows different channel materials to be integrated using a single substrate, significantly reducing manufacturing costs while maintaining the ability to create alternate doping profiles.
Solution Approach 2:
The patent changes the material parameters by using different channel materials (e.g., silicon and silicon germanium) with distinct properties. This enables the creation of stacked transistor structures with alternate doping profiles using a single substrate, avoiding the costs associated with secondary substrates.
3Productivity
If different channel materials are integrated on the same wafer, then yield and flexibility are enhanced, but the complexity of fabricating discontinuous crystalline structures increases
Solution Approach 1:
The patent segments the channel structure by introducing sacrificial ribbons that are later removed, creating discrete regions for different channel materials. This segmentation approach simplifies the fabrication of discontinuous crystalline structures while enabling the integration of different channel materials on the same wafer, thereby enhancing yield.
Solution Approach 2:
By removing the sacrificial ribbons, the patent creates well-defined interfaces between different channel materials. This extraction process simplifies the overall structure compared to attempting to grow discontinuous crystalline structures directly, reducing fabrication complexity while maintaining high yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces defects and costs by allowing for the integration of different channel materials and gate materials on the same wafer, enhancing the yield and flexibility in manufacturing stacked transistor structures with alternate doping profiles.
Implementation Method 1
the regrowth of channels from epitaxial structures
Data Source
AI summary
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrating different materials into the channels for stacked transistor devices, for example in a CFET configuration, where the bottom device is an NMOS device and the top device is a PMOS device, or vice versa. Other embodiments may be described and/or claimed.