Vertically Stacked CFET Structure Using Wafer Bonding for Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher device density, performance, and reducing costs, particularly in the fabrication and design of nanosheet FETs as transistor dimensions are scaled down.
Innovation Solution
The implementation of vertically stacked complementary field-effect transistors (CFETs) using nanosheet FETs, where a first nanosheet FET is stacked on a second nanosheet FET, with the use of wafer bonding technology to form a combinational Complementary FET (cCFET), allowing for independent choice of N/P channel properties and improved isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then production efficiency and cost are improved, but fabrication challenges and design complexity increase
Solution Approach 1:
The patent transitions from planar transistor design to three-dimensional vertically stacked nanosheet FETs. Multiple nanosheets are stacked vertically to increase device density within the same footprint, moving the solution from two-dimensional scaling to three-dimensional architecture. This dimensional change allows continued density improvement without further reducing lateral dimensions, thereby avoiding the associated fabrication challenges.
2Reliability
If vertically stacked nanosheet FETs are implemented to increase device density, then channel control is improved, but fabrication process complexity increases
Solution Approach 1:
The vertically stacked channel is segmented into multiple discrete nanosheets separated by sacrificial layers. Each nanosheet can be independently controlled by gate electrodes, improving gate control over the channel. The segmentation also allows for modular fabrication where nanosheets are formed separately and then stacked, simplifying the overall fabrication process compared to forming a single complex three-dimensional channel.
Solution Approach 2:
Sacrificial layers are introduced as intermediary structures between the nanosheets during fabrication. These sacrificial layers enable the formation of discrete nanosheets and provide separation during the stacking process. After assembly, the sacrificial layers are removed, leaving the desired vertically stacked nanosheet structure with improved gate control.
3Reliability
If wafer bonding is used to form vertically stacked CFETs, then isolation and leakage reduction are improved, but manufacturing steps increase
Solution Approach 1:
Multiple semiconductor wafers containing different transistor types (n-type and p-type) are bonded together to form a vertically stacked complementary FET structure. This merging of separate wafers achieves excellent isolation between the complementary devices and reduces leakage paths that would exist in laterally integrated structures. The bonding interface provides a natural isolation barrier.
Solution Approach 2:
The patent uses vertical stacking through wafer bonding to separate n-type and p-type devices in the vertical dimension rather than laterally. This three-dimensional arrangement provides inherent isolation between the complementary devices, eliminating the need for complex lateral isolation structures and reducing leakage paths between nFET and pFET regions.
Data Source
AI summary
Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N/P channel properties, provide a simple way to form the N/P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.