Stacked Semiconductor Channels With Recessed Gates for Short-Channel Control
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deteriorated operational properties, necessitating improved reliability and electrical characteristics.
Innovation Solution
A semiconductor device design featuring vertically stacked semiconductor patterns with a sandglass-shaped gate electrode and channel recesses, along with a method of fabrication that includes selective epitaxial growth and oxidation processes to enhance channel length and prevent short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to reduce pattern size and design rule, then device integration density increases, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns. Multiple semiconductor patterns are stacked in the vertical direction to form channel patterns with increased effective channel length. This dimensional change allows the device to achieve larger effective channel lengths without increasing the lateral footprint, thereby maintaining small pattern size while improving operational properties through enhanced channel control and reduced short channel effects.
Solution Approach 2:
The channel pattern is divided into multiple discrete semiconductor patterns stacked vertically, with gate electrodes positioned between adjacent semiconductor patterns. This segmentation creates multiple independent channel regions that can be controlled by separate gate structures, allowing for improved electrical characteristics and reduced short channel effects while maintaining compact device dimensions.
2Reliability
If channel length is increased to reduce short channel effects, then operational reliability improves, but device area increases
Solution Approach 1:
The patent utilizes the vertical dimension to extend channel length by stacking multiple semiconductor patterns vertically. The effective channel length is increased through the cumulative height of stacked channels rather than extending laterally. This approach allows for longer effective channel lengths that improve short channel effect control while maintaining compact lateral device footprints, as the channel extension occurs in the vertical stacking direction.
Solution Approach 2:
The channel is segmented into multiple discrete semiconductor patterns stacked vertically, with each pattern contributing to the effective channel length. Gate electrodes are positioned between adjacent semiconductor patterns to control each channel segment. This segmentation enables the device to achieve extended effective channel length for improved reliability without proportionally increasing the overall device area, as the channels are arranged vertically rather than horizontally.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the reliability and electrical characteristics of semiconductor devices by increasing effective channel length, reducing short channel effects, and preventing leakage currents, thereby enhancing performance.
Implementation Method 1
a gate insulating layer interposed between the first portion of the gate electrode and each of the first and second semiconductor patterns
Implementation Method 2
performing an oxidation process on the exposed semiconductor pattern to form a first oxide pattern and a second oxide pattern at lower and upper surfaces of the semiconductor pattern, respectively
Data Source
AI summary
A semiconductor device and a fabrication method thereof are disclosed. The device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of vertically-stacked semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns, the gate electrode including a first portion interposed between first and second semiconductor patterns, which are two adjacent ones of the semiconductor patterns, and a gate insulating layer interposed between the first portion of the gate electrode and the first and second semiconductor patterns. The second semiconductor pattern is located at a tier higher than the first semiconductor pattern. The first semiconductor pattern includes a first channel recess having a first depth, and the second semiconductor pattern includes a second channel recess having a second depth smaller than the first depth.