Stacked Semiconductor Chip Wiring Without Through-Electrodes
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Solution Overview
Problem
Conventional semiconductor devices face a reduction in element integration within the second element chip due to the presence of through electrodes, which also complicates mechanical strength and manufacturing processes.
Innovation Solution
A semiconductor device design featuring a lamination structure with a first element chip and a smaller second element chip, where the first element chip has a semiconductor substrate and wiring layer laminated together, and the second element chip has a similar structure with its own wiring layer, connected via external connection wires that do not penetrate the second element chip, allowing for improved integration and mechanical strength without the need for through holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through electrodes are used to electrically connect the first and second element chips, then electrical connection between chips is achieved, but element integration within the second element chip is reduced
Solution Approach 1:
The patent transitions from vertical through-electrode connections (penetrating the second chip) to lateral wire connections (extending around the chip perimeter). This dimensional shift allows electrical connection without compromising the second chip's internal element integration, as wires are routed externally rather than through the chip substrate.
Solution Approach 2:
The patent introduces external wires as intermediary connection elements that bridge the first and second element chips without requiring through electrodes in the second chip. These wires act as mediators, providing electrical connection while preserving the integrity and integration density of the second chip's internal structure.
2Reliability
If through electrodes penetrate the second element chip, then electrical connection is established, but mechanical strength is compromised
Solution Approach 1:
The connection path is relocated from the vertical dimension (through the chip thickness) to the lateral dimension (around the chip perimeter). This eliminates the need for holes through the second chip, preserving its mechanical strength while achieving electrical connection through externally routed wires.
Solution Approach 2:
The patent extracts the through-electrode function from the second element chip by routing connection wires externally. This separation removes the mechanical intrusion into the second chip, allowing it to maintain full structural integrity while still achieving the desired electrical connectivity through alternative external pathways.
3Reliability
If through electrodes are used for connection, then electrical connectivity is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent extracts the connection function from the second chip's manufacturing process by using externally attached wires rather than integrated through electrodes. This simplifies the second chip's fabrication, as it no longer requires through-hole formation, plating, and alignment steps, while the wire connections can be established in a separate, simpler post-processing step.
Data Source
AI summary
A semiconductor device capable of improving integration of elements within a second element chip is provided. A semiconductor device according to the present technology includes at least one first element chip, and at least one chip laminated with the first element chip and smaller than the first element chip. The at least one chip includes at least one second element chip. The first element chip has a laminated structure where a first semiconductor substrate and a first wiring layer are laminated. The second element chip has a laminated structure where a second semiconductor substrate and a second wiring layer are laminated. The first wiring layer and the second wiring layer are joined face-to-face with each other. The semiconductor device further includes an external connection terminal and a wire that electrically connects the first wiring layer and the external connection terminal.