Stacked-Chip Impedance Calibration Through ZQ Replica Circuits
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Solution Overview
Problem
In semiconductor devices with stacked chips connected via through electrodes, variations in wiring length lead to mismatched impedance values among chips, hindering high-speed operation and causing signal transmission errors.
Innovation Solution
A semiconductor device with a control chip and controlled chips, where a comparator circuit on the control chip adjusts the impedance of a replica output circuit using an external resistance element, ensuring consistent impedance across all chips by accounting for parasitic resistance of through electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chips are stacked closer to increase integration density, then device capacity increases, but wiring length variation and impedance mismatch worsen
Solution Approach 1:
The patent applies local quality by providing separate calibration circuits for chips at different stack positions (first calibration circuit for first-position chips, second calibration circuit for second-position chips). Each calibration circuit is optimized for its specific location's wiring characteristics, allowing impedance matching to be tailored locally rather than using a uniform approach for all chips.
Solution Approach 2:
The calibration system is segmented into position-specific calibration circuits. Instead of a single universal calibration circuit, the patent divides the calibration function into multiple independent circuits, each handling chips at specific stack positions with their unique wiring length characteristics.
2Device complexity
If a single calibration circuit is used for all chips, then device complexity is reduced, but impedance matching precision deteriorates
Solution Approach 1:
The patent implements local quality by creating position-specific calibration circuits that are optimized for the wiring characteristics of chips at their particular stack positions. This local optimization ensures accurate impedance matching for each chip position while maintaining clear functional separation between calibration circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures that all controlled chips have matched output impedances as seen from the control chip, enabling high-speed data transfer and minimizing signal errors by accurately calibrating impedance values regardless of chip location.
Implementation Method 1
a comparator circuit operable to compare a voltage of the second ZQ terminal with a reference voltage
Implementation Method 2
a second control circuit operable to perform a process according to a comparison result from the comparator circuit
Data Source
AI summary
A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit 123 which performs a process based on a comparison by the comparator circuit. The first control circuit and the second control circuit receive a common input signal to operate and sequentially change and set the impedance until the comparison result changes when an external resistance element is connected to the second ZQ terminal.