Stacked Chip Package Layout for Compact PCB Mounting and Heat Dissipation
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Solution Overview
Problem
Conventional methods for packaging MOS transistor chips require a large space on printed circuit boards due to the need for parallel connections, which is not suitable for installations with limited space.
Innovation Solution
A stacked chip package structure is developed, where two chips are stacked in a back-to-back manner with a wiring layer penetrating the encapsulant, allowing direct interconnection between inner pads and external pads, reducing the package size and improving heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple MOS transistor chips are connected in parallel on a printed circuit board, then parallel connection is achieved, but the occupied area increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of chips on a printed circuit board to a three-dimensional stacked configuration. Multiple chips are vertically stacked and interconnected through conductive vias that penetrate through the chip stack, enabling parallel connection while occupying minimal footprint area on the printed circuit board.
Solution Approach 2:
The patent implements a nested structure where multiple chip packages are stacked vertically, with each chip package containing a chip, encapsulant, and conductive vias. The conductive vias are nested within the encapsulant material, creating a compact integrated structure that reduces overall occupied area while maintaining electrical connectivity.
2Area of stationary object
If chips are stacked vertically with conductive vias penetrating encapsulant, then occupied area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the chip interconnection system into discrete modular units, where each chip package is encapsulated separately with its own set of conductive vias. This segmentation allows for standardized manufacturing processes and simplifies the overall assembly, reducing the impact of structural complexity.
3Ease of manufacture
If conventional planar connection is used, then manufacturing is simple, but heat dissipation is insufficient
Solution Approach 1:
The patent introduces vertical thermal pathways through the conductive vias that penetrate the encapsulant and connect to heat sinks or thermal management structures on the opposite side of the chip stack. This three-dimensional thermal management approach significantly improves heat dissipation efficiency compared to conventional planar heat spreaders.
Data Source
AI summary
The present disclosure describes a stacked chip package structure and a method for forming the same. In the stacked chip package structure, a third encapsulant is disposed below a first encapsulant and encapsulates a first wiring layer. The first wiring layer electrically couples a first inner pad of a first chip and a first inner pad of a second chip to a first external pad. The first wiring layer penetrates the third encapsulant and is in direct contact with the first inner pad of the first chip and the first external pad. This stacked chip package structure can save space for mounting and wiring on a printed circuit board, and the ultra-thin third wiring layer rapidly transfers the operational heat of the chips to the outside of the package structure, improving heat dissipation and enhancing device reliability.