Stacked Chip Package Structure Pillar Bump Interconnects
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Solution Overview
Problem
In semiconductor devices with embedded chips, the formation of via holes using laser beams can damage the chip electrodes, leading to reliability and yield issues and increased production costs.
Innovation Solution
A stacked chip package structure and manufacturing method involving multiple chips, pillar bumps, encapsulants, redistribution layers, and through vias, where the encapsulants expose the top surfaces of the bumps, reducing the need for conductive vias and enhancing bonding strength through roughened surfaces, thereby improving reliability and reducing production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a laser beam is used to form via holes through the insulating layer, then the via holes can be formed to electrically connect the chip electrode pad to external terminals, but the laser beam irradiation causes the Al electrode pad to fly apart and damages the semiconductor device
Solution Approach 1:
The patent introduces an intermediary protective layer (solder mask or protective film) between the laser beam and the Al electrode pad. This intermediary absorbs or reflects the laser energy, preventing direct irradiation damage to the electrode pad while still allowing via hole formation through the insulating layer. The protective layer acts as a buffer that mediates the harmful interaction between the laser beam and the sensitive electrode material.
2Reliability
If conventional via hole formation and bonding processes are used, then electrical connections can be established, but the overall thickness of the package structure increases and production costs rise
Solution Approach 1:
The patent merges multiple functions into the bump structure itself. The bumps serve simultaneously as electrical connection elements, bonding interfaces, and structural support components. By integrating these functions into a single element rather than using separate via holes, bonding layers, and support structures, the overall package thickness is reduced while maintaining reliable electrical connections.
Solution Approach 2:
The patent transitions from planar via hole connections to three-dimensional bump connections. Instead of forming horizontal via holes through insulating layers, the design uses vertical protruding bumps that extend upward from the chip surface. This dimensional change allows electrical connections to be made at the bump top surfaces, eliminating the need for thick insulating layers and complex via hole formation processes, thereby reducing overall package thickness.
3Reliability
If conventional manufacturing processes with multiple processing steps are used, then complete electrical connections can be formed, but production costs increase and manufacturing complexity rises
Solution Approach 1:
The patent performs preliminary actions by pre-forming the bump structures with integrated conductive paths and protective coatings before the final bonding process. The bumps are prepared in advance with the necessary electrical conductivity and surface properties for bonding, eliminating the need for subsequent via hole formation, conductive layer deposition, and bonding operations. This preliminary preparation simplifies the overall manufacturing process while ensuring complete electrical connections.
Data Source
AI summary
A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a second redistribution layer and a through via. The pillar bumps are disposed on a plurality of first pads of the first chip respectively. The first encapsulant encapsulates the first chip and exposes the pillar bumps. The first redistribution layer is disposed on the first encapsulant and electrically connects the first chip. The second chip is disposed on the first redistribution layer. The second encapsulant encapsulates the second chip. The second redistribution layer is disposed on the second encapsulant and electrically coupled to the second chip. The through via penetrates the second encapsulant and electrically connects the first redistribution layer and the second redistribution layer.